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A combinatorial path is the path through logic between the output of a register and the input of another register on an FPGA. A register stores data on an FPGA and updates the data on the rising edge of a clock. If the code in a combinatorial path does not execute within a clock cycle, LabVIEW returns a timing violation in the Compilation Failure dialog box.

Long combinatorial paths take more time to execute, so they limit the maximum compile rate of the FPGA VI. Long combinatorial paths are typically a problem in single-cycle Timed Loops because the logic between the output register and the input register must execute within one period of the clock rate you specify. You can minimize the number of objects on the block diagram to reduce the length of a combinatorial path. You also can use pipelining to reduce the length of a combinatorial path.

Pipelining is the process of breaking up code within a loop and dividing the code into different iterations in the same loop. Pipelining reduces the length of the combinatorial path within an iteration, so the loop can run faster while executing the same code in parallel. You can use shift registers to implement pipelining.

In the following figure, subVIs A, B, and C execute in sequence, and all of the subVIs must execute within one clock cycle because the subVIs are in a single-cycle Timed Loop.

You can use shift registers to execute subVIs A, B, and C in parallel, as shown in the following figure. In the following figure, each subVI must execute within one clock cycle.

Note  Pipelining results in an increase in latency because the output is based on the input from the previous iteration. In the figure above, subVI B uses the data from subVI A in the previous iteration and subVI C produces an output with a delay of two clock cycles compared to the previous figure.