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You can create VIs that include parallel operations. When the VI executes on a processor-based target such as Windows, LabVIEW imitates parallel operation by serially executing portions of the block diagram. In FPGA VIs, parallel operations execute simultaneously on the FPGA target because the FPGA Module creates dedicated hardware for each independent VI or function in the FPGA VI.

Parallel Operations on the FPGA

Parallel operations on the FPGA typically increase determinism and execution rate when compared to a processor-based target. Because the parallel operations no longer contend over a common resource, such as the processor LabVIEW for Windows uses, you increase determinism. Because the overall execution time of multiple operations, with dedicated hardware for each operation, is the execution time of the slowest operation, you increase execution rate. With a single hardware resource, the overall execution time for multiple operations is the sum of the execution times.

To create parallel operations, use multiple independent While Loops on a single block diagram. For example, you can implement multiple data acquisition engines, each with an independent sampling rate, as shown in the following figure.

You can use independent sampling rates to more efficiently acquire data in systems that contain both high frequency and low frequency signals. Configure one data acquisition engine with a fast sampling rate to measure a high frequency signal, such as audio signals. Configure the other data acquisition engine with a slower sampling rate to measure a low frequency signal, such as temperature.

If you use shared resources among parallel operations, you might lose the benefits of determinism and a higher execution rate. Possible shared resources include digital output lines, analog lines, memory items, the interrupt line, local and global variables, and non-reentrant subVIs.

Tip  Each parallel operation uses a certain amount of space on the FPGA. If you begin to run out of space on the FPGA and have identical parallel operations, you might save space by creating a subVI for the operation and making it non-reentrant. However, you lose parallel execution by creating a non-reentrant subVI for the operation.

SubVIs on the FPGA

LabVIEW allows you to encapsulate common sections of code as subVIs to facilitate their reuse on the block diagram. You can configure the subVI as a single instance shared among multiple callers, also known as a non-reentrant VI. You also can configure the subVI to replicate itself for each caller, also known as a reentrant VI. By default, LabVIEW subVIs are non-reentrant VIs. To change the subVI to reentrant in the subVI, select Execution from the Category pull-down menu of the VI Properties dialog box and place a checkmark in the Reentrant execution checkbox.

If you use a non-reentrant subVI in an FPGA VI, only a single copy of the subVI becomes hardware and all callers share the hardware resource. If you use a reentrant subVI in an FPGA VI, each call of the subVI generates a dedicated hardware resource. For example, if you have five instances of an event counter configured as a reentrant subVI on the block diagram, LabVIEW implements five independent copies of the event counter hardware on the FPGA.

Be careful not to use shared resources in reentrant subVIs when you want to have dedicated hardware for each copy of the subVI. If you use any shared resource in a reentrant subVI, only one copy of the shared resource exists in hardware. Each reentrant subVI must use arbitration to access the shared resource.

Although non-reentrant subVIs typically consume less space in the FPGA VI, the FPGA VI might run slower because it shares resources on the FPGA. Reentrant VIs typically consume more space in the FPGA VI, but the FPGA VI might run faster without shared resources. The following table summarizes the typical advantages and disadvantages of non-reentrant and reentrant subVIs.

Table 1. Non-Reentrant versus Reentrant SubVIs

VI Type	FPGA Speed	FPGA Utilization
Non-reentrant	Slower—Each call to the subVI waits until the previous call ends.	Lower—Only one instance of the subVI exists on the FPGA no matter how many times you use it.
Reentrant	Faster—Multiple calls to the same subVI run in parallel.	Higher—Each instance of the subVI on the block diagram uses space on the FPGA.

Transferring Data Among Parallel Loops

You can use local or global variables, target-scoped or VI-scoped FIFOs, and target-scoped or VI-scoped memory to transfer data among parallel loops. Use the FIFO Read and FIFO Write functions with target-scoped and VI-scoped FIFOs to transfer data to and from loops, such as single-cycle Timed Loops. You also can use target-scoped FIFOs to transfer data from one subVI to another in an FPGA VI. An FPGA FIFO acts like a fixed-length queue, where the first value in is the first value out. Use the FIFO Write function to put data in a FIFO. Use the FIFO Read function to retrieve the data from another loop or subVI in the FPGA VI. Use the Memory Read and Memory Write functions with target-scoped or VI-scoped memory to transfer data to and from loops within one clock domain.

FPGA FIFOs and LabVIEW queues both transfer data from one location to another. However, unlike a LabVIEW queue, an FPGA FIFO imposes a size restriction. You must configure the name, data type, and number of the FPGA FIFO element when you create a FIFO. Both the reader and the writer can access the data in an FPGA FIFO at the same time, allowing FPGA FIFOs to work properly in an FPGA VI.

LabVIEW arbitrates different accessors to the same FIFO. Each FIFO has separate arbitration for read access and write access. You can select the arbitration option in the FPGA FIFO Properties dialog box. You can select Always Arbitrate, Arbitrate if Multiple Requestors Only, or Never Arbitrate. LabVIEW globally applies the arbitration option you select to all other accessors of the same FIFO. You must select Arbitrate if Multiple Requestors Only if you use the FIFO Read or FIFO Write function in a single-cycle Timed Loop.

LabVIEW preserves the existing data when the FPGA FIFO is full. Rather than overwriting the oldest element, the FIFO Write function returns TRUE in the Full output to indicate the FPGA FIFO is full and no new data is being stored in the FIFO.

Note  Refer to Transferring Data among Multiple Clock Domains for information about transferring data among single-cycle Timed Loops configured with multiple clock domains.