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Right-click a FIFO item in the Project Explorer window or a VI-Scoped FIFO Configuration node on the block diagram and select Properties from the shortcut menu to display this dialog box.

Use this dialog box to edit properties for FIFOs.

This dialog box includes the following components:

• Name—Specifies the name of the FIFO that appears in the Project Explorer window or in the VI-Scoped FIFO Configuration node. The name also appears in the FIFO Read or FIFO Write function on the block diagram.
• Type—Specifies the type of FIFO you use. Select Target-Scoped if you want to use FIFOs to transfer data within the FPGA VI. Select Host to Target—DMA or Target to Host—DMA if you want to use FIFOs to transfer data between the host VI and target. This component is not available for VI-scoped FIFOs.
• DMA Channel—Specifies the channel to use on the FPGA target. You can use only one FIFO per DMA channel. Each FPGA target has a fixed number of DMA channels available for transferring data between the target and host computer. You can use multiple FIFO Read and FIFO Write functions to read and write to the same DMA FIFO. The number of DMA channels available depends on the FPGA target. Refer to the specific FPGA target hardware documentation for more information.
• Data Properties—Contains the following options:
  • Representation—Specifies the data type of the data that is stored in the FIFO. You can select integer or Boolean data types. This option is disabled if you select Host to Target—DMA or Target to Host—DMA from the Type pull-down menu because you can use DMA FIFOs only with unsigned 32-bit integers.
  • Memory Type—Specifies the type of storage the FIFO uses on the FPGA. This option is disabled if you select DMA from the Type pull-down menu. Contains the following options:

    Note  You cannot use FIFOs with a Memory Type of Flip-Flops or Look-Up Table across multiple clock domains.

    • Flip-Flops—Stores the data with standard flip-flops. This option stores the data using gates on the FPGA and provides the fastest performance. National Instruments recommends using this option for small FIFOs, up to 100 bytes.
    • Look-Up Table—Stores the data in look-up tables available on the FPGA. The FPGA includes two look-up tables per slice. NI recommends using this option for FIFOs less than 300 bytes in size.
    • Block Memory—Stores the data using embedded blocks of memory. Use this option for FIFOs larger than 300 bytes.

      Note  If you select the Block Memory option, you might not be able to read data in a target-scoped FIFO or VI-scoped FIFO until up to six clock cycles after you write the data to the FIFO. Use the Empty or Full output of the FIFO Read or FIFO Write function to determine when the data is ready.

  • Depth—Specifies the number of elements the FIFO can hold. The maximum number of elements the FIFO can hold depends on the Memory Type you select and the amount of space available on the FPGA for the type of memory. If the FPGA does not have enough space for the Depth you enter, the FPGA VI fails to compile and an error message appears. If you select DMA—Host to Target or DMA—Target to Host in the Type pull-down menu, Depth specifies the size, in elements, of the FPGA part of the DMA FIFO. LabVIEW coerces Depth to the next valid value for a FIFO.

    The depth of the FIFO is restricted based on its type. For FIFOs with a Type of Local and a Memory Type of Block Memory, you can use a size that is a power of two plus a small buffer of elements at the end. The buffer might fill completely or fill only partially, which leaves the FIFO size between two and four elements larger than a power of two. The FPGA FIFO Properties dialog box displays the maximum size of 2^M+4, where M is the address width of the memory block.

    For FIFOs with a Type of DMA—Host to Target or DMA—Target to Host and a Memory Type of Block Memory, you can use a size that is one less than a power of two. LabVIEW restricts access to the last element for efficiency. The FPGA FIFO Properties dialog box displays the maximum size of 2^M-1 where M is the address width of the memory block.

• Arbitration—Determines the arbitration options for the FIFO. Contains the following options:
  • Read—Sets the type of arbitration for reading the FIFO using the FIFO Read function. Do not change this option if you select DMA—Host to Target or DMA—Target to Host from the Type pull-down menu. Select Arbitrate if Multiple Requestors Only or Never Arbitrate if you use the FIFO Read function in a single-cycle Timed Loop.
  • Write—Sets the type of arbitration for writing to the FIFO using the FIFO Write function or from the host VI. Select Arbitrate if Multiple Requestors Only or Never Arbitrate if you use the FIFO Write function in a single-cycle Timed Loop.