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Right-click the base clock in the Project Explorer window and select Properties from the shortcut menu to display this dialog box.

Use the FPGA Base Clock Properties dialog box to configure an FPGA base clock associated with an FPGA target. A base clock is a digital signal existing in hardware that you can use as a clock for an FPGA Module application. A derived clock is a clock you create from a base clock that you can use as a clock for an FPGA Module application. The top-level clock is the global clock that the FPGA VI uses outside a single-cycle Timed Loop. LabVIEW uses the FPGA base clock properties when setting timing constraints on circuits generated from the FPGA VI during compilation.

The options available in this dialog box vary according to FPGA target and clock. Refer to the specific FPGA target hardware documentation for more information.

This dialog box might include the following components:

• Name—Specifies the name of the FPGA target base clock that appears in the Project Explorer window.
• Resource—Specifies the resource the FPGA target uses as the base clock.
• Nominal Frequency—Specifies the frequency of the FPGA target base clock if the clock is not variable. You can select MHz, kHz, or Hz as the unit of frequency.
• Variable Frequency—Allows you to compile an FPGA VI for a range of clock frequencies. If you place a checkmark in this checkbox, you must specify the Min Frequency and the Max Frequency of the FPGA base clock.
• Min Frequency—Specifies the minimum frequency of the FPGA target base clock. You can select MHz, kHz, or Hz as the unit of frequency.
• Max Frequency—Specifies the maximum frequency of the FPGA target base clock. You can select MHz, kHz, or Hz as the unit of frequency.
• Accuracy (ppm)—Specifies the accuracy of the FPGA target base clock in parts per million.
• Peak Period Jitter (ps)—Specifies the maximum period jitter of the FPGA target base clock in picoseconds.