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In an FPGA VI, double-click the Input Node of a Timed Loop or right-click the node and select Configure Input Node from the shortcut menu to display this dialog box.

Use this dialog box to configure options on a single-cycle Timed Loop in an FPGA VI. You can specify that a single-cycle Timed Loop uses any clock under the FPGA target in the Project Explorer window. You can have multiple single-cycle Timed Loops on a block diagram, each executing at different clock rates. Double-click the Input Node of a Timed Loop to display this dialog box.

This dialog box includes the following components:

• Loop Name—Specifies the name of the single-cycle Timed Loop in the FPGA VI. This name appears in a timing constraint failure path in the Compilation Failure dialog box.
• Top-Level Timing Source—Specifies that the single-cycle Timed Loop uses the top-level FPGA target clock.
• Select Timing Source—Allows you to select a clock other than the top-level FPGA target clock. You can select the FPGA target base clock or any FPGA target clock you derive.
• Available Timing Sources—Displays a list of the available timing sources that appear under the FPGA target in the Project Explorer window.
• Selection—Displays details about the clock you select as the single-cycle Timed Loop clock.

The base clock is a digital signal existing in hardware that you can use as a clock for an FPGA Module application. The derived clock is a clock you create from a base clock that you can use as a clock for an FPGA Module application. The top-level clock is the global clock that the FPGA VI uses outside a single-cycle Timed Loop.