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Right-click an FPGA target base clock in the Project Explorer window and select New FPGA Derived Clock from the shortcut menu to display this dialog box.

A base clock is a digital signal existing in hardware that you can use as a clock for an FPGA Module application. A derived clock is a clock you create from a base clock that you can use as a clock for an FPGA Module application. The top-level clock is the global clock that the FPGA VI uses outside a single-cycle Timed Loop.

Use the FPGA Derived Clock Properties dialog box to configure FPGA target derived clocks. You can scale the frequency of an FPGA target base clock by using a derived clock. If you do not know if the FPGA target supports the frequency you want to use, enter a value in the Desired Derived Frequency and read the resulting Message text. LabVIEW selects a supported clock using the equation in the Actual Derived Configuration and determines a Derived Frequency as close as possible to the Desired Derived Frequency. If the FPGA target supports the Desired Derived Frequency, the Message text box displays Valid Configuration. You also can enter values in the Multiplier and Divisor text boxes to determine a supported Derived Frequency.

Support for FPGA target derived clocks varies according to FPGA target. Refer to the specific FPGA target hardware documentation for more information.

This dialog box includes the following components:

• Name—Specifies the name of the FPGA target derived clock that appears in the Project Explorer window.
• Parent Clock Name—Specifies the name of the base clock from which the derived clock was created.
• Desired Derived Frequency—Specifies the frequency you want the FPGA target derived clock to use.
• Units—Specifies the units for the derived clock frequency. You can select MHz (default), kHz, or Hz.
• Actual Derived Configuration—Displays an equation you can use to determine the frequency of the FPGA target derived clock. This section includes the following options:
  • Parent Frequency (Hz)—Displays the frequency of the FPGA target base clock from which you derive the new clock.
  • Multiplier (1 - 32)—Specifies the numerator of the number by which you multiply the Parent Frequency (Hz) to determine the derived frequency of the FPGA target derived clock. You can use an integer that is greater than or equal to 1 and less than or equal to 32.
  • Divisor (1 - 32)—Specifies the denominator of the number by which you multiply the Parent Frequency (Hz) to determine the derived frequency of the FPGA target derived clock. You can use an integer that is greater than or equal to 1 and less than or equal to 32.
  • Derived Frequency (Hz)—Displays the frequency of the resulting derived clock, in Hertz.
  • Parent Period (s)—Displays the period of the parent FPGA target clock, in seconds.
  • Derived Period (s)—Displays the period of the FPGA target derived clock, in seconds.
• Message—Displays information about the FPGA target derived clock.