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Select Advanced Code Generation in the Category list of the FPGA I/O Properties dialog box to display this page.

Use this page to select code generation options, such as arbitration and the number of synchronizing registers. You also can specify certain I/O options in the FPGA I/O Node Properties dialog box. Supported options, values, and defaults vary according to FPGA target and FPGA I/O. This page displays only the options and values supported by the selected FPGA I/O. Some FPGA targets might not allow access to this page at all. Refer to the specific FPGA target hardware documentation for more information.

This page can contain the following options:

• Arbitration for Input Data—Specifies the type of arbitration the resource uses for input data. This option typically applies to FPGA I/O items where input requires multiple clock cycles. This option can include Always Arbitrate, Arbitrate if Multiple Requestors Only, and Never Arbitrate.
• Arbitration for Output Data—Specifies the type of arbitration the resource uses for output data. This option can include Always Arbitrate, Arbitrate if Multiple Requestors Only, and Never Arbitrate.
• Arbitration for Output Enable—Specifies the type of arbitration the resource uses for output enable. This option appears for FPGA I/O with output enable, such as bidirectional digital I/O. This option can include Always Arbitrate, Arbitrate if Multiple Requestors Only, and Never Arbitrate.
• Number of Synchronizing Registers for Output Data—Specifies the number of synchronizing registers between the FPGA I/O function executing on the FPGA target and the FPGA target hardware interface. The FPGA target hardware interface might be a physical I/O connector on the device or a connection to a section of the FPGA that contains circuitry designed by National Instruments. Each synchronization register executes in one clock cycle.

  Caution  Select 0 only if you also use the HDL Interface Node and the HDL code contains its own synchronization registers.

  Supported options typically include the following:

  • 0—Specifies that the FPGA VI uses no synchronization registers. Do not select this option for most FPGA Module applications.
    
    

    Note  If you select 0 for digital input and digital output resources in a single-cycle Timed Loop, you create a combinatorial circuit between the two resources. The combinatorial circuit might cause glitches on the output signal.

  • 1—Specifies that the FPGA VI uses one synchronizing register between the FPGA I/O resource and the FPGA target hardware interface.
• Number of Synchronizing Registers for Output Enable—Specifies the number of synchronizing registers between the FPGA I/O Node executing on the FPGA target and the FPGA target hardware interface. This option appears for FPGA I/O with the Set Output Enable method available, such as bidirectional digital I/O.

  Each synchronization register executes in one clock cycle.

  Caution  Select 0 only if you also use the HDL Interface Node and the HDL code contains its own synchronization registers.

  Supported options typically include the following:

  • 0—Specifies that the FPGA VI uses no synchronization registers. Do not select this option for most FPGA Module applications.
    
    

    Note  If you select 0 for digital input and digital output resources in a single-cycle Timed Loop, you create a combinatorial circuit between the two resources. The combinatorial circuit might cause glitches on the output signal.

  • 1—Specifies that the FPGA VI uses one synchronizing register between the FPGA I/O resource and the FPGA target hardware interface.