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Select Advanced Code Generation in the Category list of the FPGA I/O Node Properties dialog box to display this page.

Use this page to select code generation options, such as the number of synchronizing registers. Supported options, values, and defaults depend on the FPGA target and FPGA I/O you use. This page displays only the options and values supported for the selected FPGA I/O. Some FPGA targets and FPGA I/O nodes might not allow access to this page at all. Refer to the specific FPGA target hardware documentation for more information.

This page can contain the following option:

• Number of Synchronizing Registers for Read—Specifies the number of synchronizing registers between the FPGA target hardware interface and the FPGA I/O Node executing on the FPGA target. The FPGA target hardware interface might be a physical I/O connector on the device or a connection to a section of the FPGA that contains circuitry designed by National Instruments. Each synchronizing register executes in one clock cycle. If you use the FPGA I/O Node outside a single-cycle Timed Loop, LabVIEW adds one additional synchronizing register, or holding register, that attempts to hold the digital value constant for subsequent operations in the FPGA VI. If you use the FPGA I/O Node inside a single-cycle Timed Loop, LabVIEW does not add the holding register because logic inside a single-cycle Timed Loop executes every clock cycle.

  Caution  Select 0 only if you also use the HDL Interface Node and the HDL code contains its own synchronization registers. Otherwise, you might introduce metastable data in the FPGA VI and experience unpredictable behavior.

  Supported options typically include the following:

  • Auto—Specifies that the number of synchronizing registers is determined based on whether the FPGA I/O Node is in a single-cycle Timed Loop. If the FPGA I/O Node is in a single-cycle Timed Loop, the function has two synchronization registers. If not, the function has one synchronization register and one holding register.
  • 0—Specifies that the FPGA VI uses no synchronizing registers if the FPGA I/O Node is inside a single-cycle Timed Loop. If the FPGA I/O Node is outside a single-cycle Timed Loop, this option specifies that the FPGA VI uses one holding register. Do not select this option for most FPGA Module applications.
    
    

    Note  If you select 0 for digital input and digital output resources in a single-cycle Timed Loop, you create a combinatorial circuit between the two resources. The combinatorial circuit might cause glitches on the output signal.

  • 1—Specifies that the FPGA VI uses one synchronizing registers between the FPGA I/O resource and the FPGA target hardware interface if the FPGA I/O Node is inside a single-cycle Timed Loop. If the FPGA I/O Node is outside a single-cycle Timed Loop, this option specifies that the FPGA VI uses one synchronizing register and one holding register.

    Note  You might encounter metastable data if the FPGA I/O Node is in a single-cycle Timed Loop and set with this option when the data is not already synchronized to the clock of the single-cycle Timed Loop.

  • 2—Specifies that the FPGA VI uses two synchronizing registers between the FPGA I/O resource and the FPGA target hardware interface if the FPGA I/O Node is inside a single-cycle Timed Loop. If the FPGA I/O Node is outside a single-cycle Timed Loop, this option specifies that the FPGA VI uses two synchronizing registers and one holding register. Select this option to avoid metastability if the value of the input to the FPGA I/O Node read element might change while the FPGA I/O Node samples the FPGA target hardware interface. If you select this option for an FPGA I/O Node within a single-cycle Timed Loop, you have no metastable data in the FPGA VI.