You must compile an FPGA VI before you can run it on an FPGA target. You can compile FPGA VIs in the following ways:
![]() |
Note You must be targeted on an FPGA target to compile an FPGA VI. You cannot compile an FPGA VI with an FPGA target emulator. |
LabVIEW uses the LabVIEW FPGA Compile Server to compile FPGA VIs. Compiling FPGA VIs can take from a few minutes to a few hours. Consider testing and debugging an FPGA VI before you compile it.
![]() |
Tip You can compile FPGA VIs on a remote computer. You also can disconnect from the LabVIEW FPGA Compile Server and return to LabVIEW during the compile process. |
The LabVIEW FPGA Compile Server launches automatically when you run an FPGA VI that is not compiled or that you modified since the last compile. LabVIEW converts the VI into intermediate files to send to the LabVIEW FPGA Compile Server. The LabVIEW FPGA Compile Server converts the intermediate files into a bitfile. LabVIEW saves the compiled bitfile in a subdirectory of the same directory in which you saved the project.
When you run an FPGA VI using Interactive Front Panel Communication, LabVIEW automatically downloads the bitfile to the FPGA target unless the VI is already loaded. Support of Interactive Front Panel Communication varies by FPGA target. Refer to the specific FPGA target hardware documentation for more information.
You can open a reference to an FPGA VI or a specific bitfile from host VIs with the Open FPGA VI Reference function for Programmatic FPGA Interface Communication. If you do not have the FPGA Module or you distribute an FPGA VI to a LabVIEW user without the FPGA Module, you must open a reference to the specific bitfile in the host VI. However, National Instruments recommends you open a reference to the FPGA VI rather than a specific bitfile for most applications.
![]() |
Caution Downloading or running an FPGA VI on an FPGA target might cause output lines on the FPGA target to change. Make sure the possible output line changes do not damage the equipment connected to the FPGA target. If the output line changes could damage equipment, use an FPGA target in the Project Explorer window that is not associated with a specific physical FPGA target. |