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Complete the following steps to force a loop in an FPGA VI to execute at a specific time interval.

1. Place a While Loop on the block diagram.
   
   
2. Right-click the conditional terminal of the While Loop and select either Create Constant or Create Control from the shortcut menu depending on the needs of the application.
3. Place a Flat Sequence structure inside the While Loop.
   
   
4. Place a Loop Timer VI inside the Flat Sequence structure.
   
   
5. Configure the Loop Timer in the Configure Loop Timer dialog box and click the OK button.
6. Right-click the Count input terminal of the Loop Timer VI and select Create»Constant. Enter the amount of time you want to elapse between iterations of the While Loop.
7. Right-click the Flat Sequence structure and select Add Frame After from the shortcut menu.
8. Place the code you want to execute on the FPGA in the new frame of the Flat Sequence structure. The code must be able to execute in less time than the amount of time you specified in step 6. If the code takes longer than the time specified, the execution time of the code determines the loop rate, and overrides the loop rate you specified in step 6.