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Opens a reference to the FPGA VI or bitfile and FPGA target you select in the shortcut menu or that you specify with the resource name input. You must open a reference to the FPGA target before you can communicate between the host VI and the FPGA VI. Details  

	error in describes error conditions that occur before this VI or function runs. The default is no error. If an error occurred before this VI or function runs, the VI or function passes the error in value to error out. This VI or function runs normally only if no error occurred before this VI or function runs. If an error occurs while this VI or function runs, it runs normally and sets its own error status in error out. Use the Simple Error Handler or General Error Handler VIs to display the description of the error code. Use error in and error out to check errors and to specify execution order by wiring error out from one node to error in of the next node. status is TRUE (X) if an error occurred before this VI or function ran or FALSE (checkmark) to indicate a warning or that no error occurred before this VI or function ran. The default is FALSE. code is the error or warning code. The default is 0. If status is TRUE, code is a nonzero error code. If status is FALSE, code is 0 or a warning code. source specifies the origin of the error or warning and is, in most cases, the name of the VI or function that produced the error or warning. The default is an empty string.
	FPGA VI Reference Out returns a reference to the FPGA VI running on the FPGA target. You can bind the FPGA VI Reference Out parameter to type definitions so that LabVIEW automatically propagates configuration changes to subsequent subVIs in the data flow.
	error out contains error information. If error in indicates that an error occurred before this VI or function ran, error out contains the same error information. Otherwise, it describes the error status that this VI or function produces. Right-click the error out front panel indicator and select Explain Error from the shortcut menu for more information about the error. status is TRUE (X) if an error occurred or FALSE (checkmark) to indicate a warning or that no error occurred. code is the error or warning code. If status is TRUE, code is a nonzero error code. If status is FALSE, code is 0 or a warning code. source describes the origin of the error or warning and is, in most cases, the name of the VI or function that produced the error or warning.

Open FPGA VI Reference Details

Place and wire a Close FPGA VI Reference function for every Open FPGA VI Reference function in a host VI. When the Open FPGA VI Reference function first executes on the block diagram, it checks whether the compiled FPGA VI already exists on the FPGA target. If the compiled FPGA VI is not on the FPGA target, the Open FPGA VI Reference function downloads the compiled FPGA VI to the FPGA target. If you select Open and Run from the shortcut menu, the FPGA VI starts running if it is not already running.

The Open FPGA VI Reference function does not affect the FPGA VI if it is already downloaded and running. If you want to restart the FPGA VI, you can use the Invoke Method function to abort or reset the FPGA VI and use the Invoke Method function to run the FPGA VI again.

Caution  Open only one reference to an FPGA VI or a bitfile on one FPGA target at a time, and close one reference before opening another. Opening multiple references to FPGA VIs or bitfiles on the same physical target might cause erroneous behavior without any error messages.

Note  The Open FPGA VI Reference function extracts the bitstream from the compiled FPGA VI or bitfile and stores the bitstream when you save the host VI. The bitstream contains the programming instructions LabVIEW downloads to the FPGA target.

Use the Open FPGA VI Reference function to do the following:

• Select the FPGA VI or bitfile with which the host VI communicates.
• Select the FPGA target on which the FPGA VI runs.
• Determine whether the host VI opens and runs the FPGA VI or just opens the FPGA VI.

Selecting the FPGA VI or Bitfile

To determine the VI that the Open FPGA VI Reference function opens, drag the FPGA VI from the Project Explorer window onto the Open FPGA VI Reference function. You also can right-click the Open FPGA VI Reference function, select Select VI from the shortcut menu, and navigate to the FPGA VI. To determine the bitfile that the function opens, right-click the Open FPGA VI Reference function and select Select Bitfile from the shortcut menu.

Selecting the FPGA Target

LabVIEW might automatically determine the FPGA target on which the FPGA VI runs based on the information in the project, depending on the FPGA target.

Some FPGA targets allow you to select the FPGA target in a separate step by right-clicking the Open FPGA VI Reference function and selecting Select Address from the shortcut menu. On such targets, you also can programmatically determine the FPGA target on which you want to run the FPGA VI with the resource name input. To use the resource name input, right-click the Open FPGA VI Reference function and select Show Resource Input from the shortcut menu. Wire the resource name input to a control or constant supported by the FPGA target.

Other FPGA targets require you to select the FPGA target programmatically using the resource name input. On such targets, wire the resource name input to a control or constant supported by the FPGA target.

Note  You must compile the FPGA VI before the Open FPGA VI Reference function can download or run the VI on the FPGA target.

Determining the Open Behavior

By default for some FPGA targets, this function opens and runs the compiled FPGA VI on the FPGA target if it is not already running. To open a reference to the FPGA VI without running it, right-click the Open FPGA VI Reference function on the block diagram and select Open from the shortcut menu. You then can run the FPGA VI using the Invoke Method function.

Other targets do not allow you to run the FPGA VI when you open it.

You can always run the FPGA VI from the host VI using the Invoke Method function.

Refer to the specific FPGA target hardware documentation for information about the supported behavior of the Open FPGA VI Reference function.