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FPGA Module Concepts



LabVIEW FPGA Overview

FPGA Module Application Development
Unsupported LabVIEW Features
Managing FPGA Applications in the Project Explorer Window
Configuring and Accessing Remote FPGA Targets

Creating FPGA VIs

Performing FPGA I/O

Customizing I/O
Controlling I/O Power-On States
Filtering FPGA I/O

Using Parallel Operations

Transferring Data Among Parallel Loops

Managing Shared Resources

Understanding Arbitration Options
Avoiding Jitter Due to Resource Contention
Timing FPGA VIs with Arbitration Enabled

Importing HDL Code into FPGA VIs

Including External HDL Code in the HDL Interface Node
Defining Inputs and Outputs on the HDL Interface Node
Execution Control and Enable Chain Signals for HDL Code
Controlling Execution of the HDL Interface Node
Writing HDL Code to Adapt to Multiple Clock Rates

Timing FPGA VIs

Using the FPGA Timing Functions
Executing Code in a Single FPGA Target Clock Cycle
Changing the Top-Level FPGA Target Clock Rate
Implementing Multiple Clock Domains

Reusing FPGA Objects

Using SubVIs on the FPGA

Using the Fixed-Point Data Type

Optimizing FPGA VIs for Speed and Size

Understanding Registers
Reducing Combinatorial Paths in FPGA VIs
Pipelining to Optimize FPGA VIs
Using Single-Cycle Timed Loops to Optimize FPGA VIs
Avoiding Arbitration to Optimize FPGA VIs
Limiting the Number of Front Panel Objects in FPGA VIs
Using the Smallest Data Type to Optimize FPGA VIs
Avoiding Large VIs and Functions in FPGA VIs When Possible
Using Boolean Operations to Optimize Comparisons

Controlling and Monitoring FPGA VIs

Interactive Front Panel Communication
Programmatic FPGA Interface Communication

Transferring Data Between the FPGA and the Host VI
Synchronizing the FPGA and the Host VI

Compiling and Running FPGA VIs

Using the LabVIEW FPGA Compile Server
Downloading Compiled FPGA VIs to the FPGA Target
Running Compiled FPGA VIs