You are here: NI Home > Support > Product Reference > Manuals > LabVIEW FPGA Module 8.5 Help

This topic contains detailed information about the objects on the Data Manipulation Functions palette.

Note  The information in this topic is subject to change with each version of the LabVIEW FPGA Module.

The details in the following table apply to all the Data Manipulation functions, except the Logical Shift, Rotate, and Split Number functions.

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	The Data Manipulation functions require no clock cycles to execute because they do not include internal registers.
Resources	The Data Manipulation functions consume no logic resources on the FPGA because they are purely wiring operations.

Logical Shift

Single-Cycle Timed Loop	Supported.
Usage	The logical shift operation shifts all bits including the sign bit of a signed integer. To preserve the sign of a signed integer, use the Scale By Power of 2 function.
Timing	Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register.
Resources	This function requires logic resources proportional to the number of bits in x.

Rotate

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register.
Resources	This function requires logic resources proportional to the number of bits in x.

Split Number

Single-Cycle Timed Loop	Supported.
Usage	You cannot wire an array or cluster to this function in an FPGA VI.
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function consumes no logic resources on the FPGA because it is purely a wiring operation.