You are here: NI Home > Support > Product Reference > Manuals > LabVIEW FPGA Module 8.5 Help

Reads the oldest element in an FPGA FIFO and removes the element from the FIFO.

Details  

	Timeout inputs the number of clock ticks the function waits for available data in the FIFO if the FIFO is empty. The default is 0, or no wait. A value of –1 prevents the function from timing out, so the function completes execution only when data is available for reading.
	Element returns the oldest data element in the FIFO. The Element data type is the data type you configure in the FPGA FIFO Properties dialog box when you create the FIFO. If the FIFO is empty, Element is undefined.
	Timed Out? returns TRUE if an element is not available in the FIFO before the function completes execution. If Timed Out? is TRUE, Element is undefined.

FIFO Read Details

To read from or write to FIFOs with the FIFO Read and FIFO Write functions, you must create FIFO items. You can create a FIFO item in the Project Explorer window or using the VI-Scoped FIFO Configuration node. You then can right-click the FIFO Read or FIFO Write function and select the FIFO item from the Select FIFO shortcut menu.

Tip  You can click a FIFO item in the Project Explorer window and drag it onto the block diagram to place a FIFO Read or FIFO Write function on the block diagram. You also can right-click the FIFO Read function and select Find Item in Project from the shortcut menu to highlight the FIFO item in the Project Explorer window.

Right-click the FIFO Read function and select Add New FIFO from the shortcut menu to create a new target-scoped or DMA FIFO.

You can use the FIFO Read function with DMA FIFOs to transfer data to host VIs.

To clear target-scoped or VI-scoped FIFOs on the FPGA, use the FIFO Clear function. To clear DMA FIFOs from the host VI, use the Stop method on the Invoke Method function.

Special Considerations for Single-Cycle Timed Loops

If you use the FIFO Read function in a single-cycle Timed Loop, you must set the Read option in the FPGA FIFO Properties dialog box to Arbitrate if Multiple Requestors Only or Never Arbitrate for the FIFO item you read, and you cannot use the function with that FIFO anywhere else in the FPGA VI. You also must wire a constant of 0 to Timeout.

You can use FIFOs to transfer data among multiple clock domains.

Error Handling Details

Add error terminals to be sure the data you receive is valid. Right-click the FIFO Read function and select Show Error Terminals from the shortcut menu to add standard LabVIEW error in and error out parameters to the function. If error in includes an error, you might receive incorrect data.

Note  Adding error in and error out parameters increases the amount of space the function uses on the FPGA target. The error in and error out parameters also can cause slower execution on the FPGA target.