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Writes an element to an FPGA FIFO.

Details  

	Element inputs the data element you want to store in the FIFO.
	Timeout inputs the number of clock ticks the function waits for available space in the FIFO if the FIFO is full. The default is 0, or no wait. A value of –1 prevents the function from timing out. Wire a constant of zero to Timeout if you use the FIFO Write function in a single-cycle Timed Loop.
	Timed Out? returns TRUE if space in the FIFO is not available before the function completes execution. If Timed Out? is TRUE, the function does not add Element to the FIFO.

FIFO Write Details

To read from or write to FIFOs with the FIFO Read and FIFO Write functions, you must create FIFO items. You can create a FIFO item in the Project Explorer window or using the VI-Scoped FIFO Configuration node. You then can right-click the FIFO Read or FIFO Write function and select the FIFO item from the Select FIFO shortcut menu.

Tip  You can click a FIFO item in the Project Explorer window and drag it onto the block diagram to place a FIFO Read or FIFO Write function on the block diagram. You also can right-click the FIFO Write function and select Find Item in Project from the shortcut menu to highlight the FIFO item in the Project Explorer window.

Right-click the FIFO Write function and select Add New FIFO from the shortcut menu to create a new target-scoped or DMA FIFO.

You can use the FIFO Write function with DMA FIFOs to transfer data to host VIs.

To clear target-scoped or VI-scoped FIFOs on the FPGA, use the FIFO Clear function. To clear DMA FIFOs from the host VI, use the Stop method on the Invoke Method function.

Special Considerations for Single-Cycle Timed Loops

If you use the FIFO Write function in a single-cycle Timed Loop, you must set the Write option in the FPGA FIFO Properties dialog box to Arbitrate if Multiple Requestors Only or Never Arbitrate for the FIFO item you write, and you cannot use the function on that FIFO anywhere else in the FPGA VI.

Error Handling Details

If an error occurs, you might receive incorrect data. Add error terminals to be sure the data you receive is valid. Right-click the FIFO Write function and select Show Error Terminals from the shortcut menu to add standard LabVIEW error in and error out parameters to the function.

Note  Adding error in and error out parameters increases the amount of space the function uses on the FPGA target. The error in and error out parameters also can cause slower execution on the FPGA target.