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Square Wave Generator (FPGA Module)

LabVIEW 8.5 FPGA Module Help
August 2007

NI Part Number:
371599C-01

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Generates a point-by-point square wave using direct digital synthesis (DDS). The synthesis runs continuously using the block diagram clock rate to produce a real-time frequency. The block diagram clock rate is the top-level clock rate, unless the Square Wave Generator Express VI is inside a single-cycle Timed Loop configured with a different clock rate.

Details  

Dialog Box Options
Block Diagram Inputs
Block Diagram Outputs

Dialog Box Options

ParameterDescription
Square Wave ParametersContains the following options:
  • Frequency—Specifies the desired output frequency in Hz.
  • Phase offset—Specifies the desired phase, in degrees, of the point in the period where the wave resets when initialize is TRUE.
  • Duty cycle—Specifies the desired percentage of time the square wave remains high over one period. The default is 50%.
  • Frequency (scaled)—Returns the scaled output frequency. The VI calculates this value using the following formula:

    Frequency (scaled) = [(Frequency/ FPGA clock rate) * 232]

    [ ] = rounded to the nearest integer

    Each call to the VI samples the current value.
  • Phase offset (scaled)—Returns the scaled phase offset. The VI calculates this value using the following formula:

    Phase offset (scaled) = [(Phase offset / 360) * 232]

    [ ] = rounded to the nearest integer

  • Duty cycle (scaled)—Returns the scaled percentage of time the square wave remains high over one period. The VI calculates this value using the following formula:

    Duty cycle (scaled) = [(Duty cycle / 100) * 232]

    [ ] = rounded to the nearest integer

OutputContains the following options:
  • Data type—Specifies the data type of the square wave. If you select Boolean, the Amplitude and Offset options are not available.
  • Amplitude—Specifies the amplitude of the square wave. The default is 32767, so square wave out is either –32767 or 32767. Refer to the Details section for more information.
  • Offset—Specifies the DC offset of the square wave. The default is 0. Refer to the Details section for more information.
Execution ModeContains the following options:
  • Inside single-cycle Timed Loop—Guarantees that the VI executes in one cycle. If you select the Inside single-cycle Timed Loop option and place the VI outside a single-cycle Timed Loop, the Code Generation Errors window reports an error.
  • Outside single-cycle Timed Loop—Returns an output each time the VI detects an edge. If you select the Outside single-cycle Timed Loop option and place the VI inside a single-cycle Timed Loop, the Code Generation Errors window reports an error.

    If you configure the VI to execute outside a single-cycle Timed Loop, the time it takes to return the VI depends on the frequency, so you also can use the VI to control the loop rate.
ClockContains the following options:
  • FPGA clock rate—Specifies the design clock rate at which the LabVIEW FPGA Compile Server builds the Square Wave Generator Express VI. Use the FPGA clock rate parameter to modify the square wave shown in the Signal Output Preview. After the Signal Output Preview displays the square wave you want, verify that the FPGA clock rate matches the block diagram clock rate. If the FPGA clock rate parameter does not match the block diagram clock rate when you compile, the Code Generation Errors window reports an error. Use the Top-Level Clock FPGA Target Properties page to change the block diagram clock rate. If the Square Wave Generator VI is inside a single-cycle Timed Loop, use the Configure Timed Loop dialog box or Source Name input on the Timed Loop to change the block diagram clock rate.
  • Set to top-level clock rate—Sets the FPGA clock rate to the top-level clock rate.
Signal Output PreviewDisplays a preview of the configured square wave.

Block Diagram Inputs

ParameterDescription
initializeSets the VI to the initial state determined by phase offset (scaled). The VI initializes automatically when it first runs.
frequency (scaled)Specifies the scaled output frequency according to the following formula:

frequency (scaled) = [(frequency (Hz)/ FPGA clock rate) * 232]

[ ] = rounded to the nearest integer

To save FPGA resources, leave the frequency (scaled) input unwired and use the configuration dialog box to specify the frequency. If you change the value of the frequency (scaled) input at run time, the square wave updates on the next call. If you change the frequency, the DDS preserves the position in the period so only the rate changes on the next call.
phase offset (scaled)Specifies the scaled phase offset according to the following formula:

phase offset (scaled) = [(phase offset (deg) / 360) * 232]

[ ] = rounded to the nearest integer

To save FPGA resources, leave the phase offset (scaled) input unwired and use the configuration dialog box to specify the phase offset. If you change the value of the phase offset (scaled) input at run time, the square wave updates on the next call. To avoid glitch conditions, do not change the value of the phase offset (scaled) input by more than the value of the frequency (scaled) input for each call to the VI.
duty cycle (scaled)Specifies the scaled duty cycle according to the following formula:

duty cycle (scaled) = [(duty cycle (%) / 100) * 232]

[ ] = rounded to the nearest integer

To save FPGA resources, leave the duty cycle (scaled) input unwired and use the configuration dialog box to specify the duty cycle. If you change the value of the duty cycle (scaled) input at run time, the square wave updates on the next period edge.
amplitudeSpecifies the amplitude of the square wave. The default is 32767, so square wave out is either –32767 or 32767.
offsetSpecifies the DC offset of the square wave. The default is 0.

Block Diagram Outputs

ParameterDescription
square wave outReturns a Boolean or an 8-, 16-, or 32-bit integer containing the square wave output. If the Square Wave Generator Express VI is inside a single-cycle Timed Loop, square wave out is a sample point. If the Square Wave Generator Express VI is outside a single-cycle Timed Loop, square wave out is a level representing the edges.

Square Wave Generator Details

Amplitude is the distance between the offset and peak. In the following example, the offset is 5 and the amplitude is 10.

To pass the square wave to an output line, you can wire square wave out to an I/O resource using the FPGA I/O Node.

Over time, the Express VI returns the expected period length and frequency. However, some jitter might occur. For example, suppose you want to create a 6.25 MHz square wave using a 40 MHz top-level clock. In this case, a clock cycle is 25 ns and a square wave period is 160 ns, so the average square wave period should be 6.4 clock cycles long. Each square wave period is an integer number of cycles, but the Express VI returns period lengths of 6, 6, 6, 7, and 7. As a result, the average period length is 6.4 clock cycles, and the average frequency is 6.25 MHz.

If you place the VI outside a single-cycle Timed Loop and run the VI with an FPGA target emulator, the timing is not precise. So, the VI returns a square wave that alternates between the high and low value.


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