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This topic contains detailed information about the objects on the Numeric Functions palette.

Note  The information in this topic is subject to change with each version of the LabVIEW FPGA Module.

Absolute Value

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and quantization modes might impact timing.
Resources	This function requires logic resources proportional to the number of bits in x. If you use this function with the fixed-point data type, the overflow and quantization modes might impact resources.

Add

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x or y, whichever data type is larger. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and quantization modes might impact timing.
Resources	This function requires logic resources proportional to the number of bits in x or y, whichever data type is larger. If you use this function with the fixed-point data type, the overflow and quantization modes might impact resources.

Compound Arithmetic

Single-Cycle Timed Loop	Supported.
Usage	You cannot wire an array or cluster to this function in an FPGA VI.
Timing	This function creates a logic tree between the inputs and the output. The number of levels in the logic tree corresponds to the logarithm (base 2) of the number of inputs, N. Each level of the logic tree performs operations in parallel, using dedicated logic resources for each operation. The first level of the tree performs ~N/2 operations and each successive level operates on the outputs of the previous level. Because the operations on each level of the tree execute simultaneously, the combinatorial logic delay corresponds to the logarithm (base 2) of N. Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the FPGA Module compiler does not place internal registers between levels of the logic tree, which can lead to long combinatorial paths. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, the FPGA Module compiler places internal registers between levels of the logic tree. The number of internal registers used by this function depends on the operation you select and the number and type of inputs you wire to the function. For addition operations, the compiler places a register after every five levels of the logic tree. For multiplication operations, the compiler places a register after every level of the logic tree if the width of the inputs is greater than 16 bits or after every two levels if the width of the inputs is 16 bits or less. For Boolean operations, the compiler places a register after every 10 levels of the logic tree.
Resources	This function consumes logic resources in proportion to the number of inputs, N. Each operation receives dedicated hardware and the total number of operations is always N - 1.

Decrement

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and quantization modes might impact timing.
Resources	This function requires logic resources proportional to the number of bits in x. If you use this function with the fixed-point data type, the overflow and quantization modes might impact resources.

Enum Constant

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	This function requires no clock cycles to execute and never includes an internal register.
Resources	This function alone consumes no logic resources on the FPGA. However, when you wire the constant to a logical operation, the constant uses FPGA lookup table resources.

Increment

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and quantization modes might impact timing.
Resources	This function requires logic resources proportional to the number of bits in x. If you use this function with the fixed-point data type, the overflow and quantization modes might impact resources.

Multiply

Single-Cycle Timed Loop	Supported.
Usage	Most FPGA targets contain a limited number of embedded multipliers. The FPGA Module compiler uses embedded multipliers to implement multiply operations until it occupies all the embedded multipliers. If the FPGA target runs out of embedded multipliers, the compiler uses generic logic gates instead, and the Multiply function becomes expensive in terms of FPGA resource usage.
Timing	Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x or y, whichever data type is larger. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and quantization modes might impact timing.
Resources	This function requires logic resources proportional to the number of bits in x or y, whichever data type is larger. Consider using the smallest data type possible to optimize FPGA VIs. If you use this function with the fixed-point data type, the overflow and quantization modes might impact resources.

Negate

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and quantization modes might impact timing.
Resources	This function requires logic resources proportional to the number of bits in x. If you use this function with the fixed-point data type, the overflow and quantization modes might impact resources.

Numeric Constant

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function alone consumes no logic resources on the FPGA. However, if you wire a Numeric constant to a logical operation, FPGA lookup table resources store the constant value.

Quotient & Remainder

Single-Cycle Timed Loop	Not supported.
Usage	You cannot wire an array or cluster to this function in an FPGA VI. Division is a relatively expensive operation on the FPGA in terms of both resource usage and time. Use the Scale By Power of 2 function with n wired as a negative constant to increase efficiency when dividing by a power of two.
Timing	This function requires clock cycles and registers in proportion to the number of bits in x or y, whichever data type is larger. Each clock cycle corresponds to one register.
Resources	This function requires logic resources proportional to the number of bits in x or y, whichever data type is larger.

Ring Constant

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	This function requires no clock cycles to execute because it does not include an internal register.
Resources	This function alone consumes no logic resources on the FPGA because it is purely a wiring operation.

Round Toward -Infinity

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. The overflow and quantization modes might impact timing.
Resources	This function requires logic resources proportional to the number of bits in x. The overflow and quantization modes might impact resources.

Round Toward +Infinity

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. The overflow and quantization modes might impact timing.
Resources	This function requires logic resources proportional to the number of bits in x. The overflow and quantization modes might impact resources.

Round To Nearest

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. The overflow and quantization modes might impact timing.
Resources	This function requires logic resources proportional to the number of bits in x. The overflow and quantization modes might impact resources.

Scale By Power of 2

Single-Cycle Timed Loop	Supported.
Usage	If you wire a constant directly to the n input, this function uses no space on the FPGA and requires no clock cycles.
Timing	Inside single-cycle Timed Loop—If n is not a constant and you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop—If n is not a constant and you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register.
Resources	If n is not a constant, this function requires FPGA logic resources in proportion to the number of bits in x.

Sign

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and quantization modes might impact timing.
Resources	This function requires logic resources proportional to the number of bits in x. If you use this function with the fixed-point data type, the overflow and quantization modes might impact resources.

Subtract

Single-Cycle Timed Loop	Supported.
Usage	N/A
Timing	Inside single-cycle Timed Loop—When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x or y, whichever data type is larger. Outside single-cycle Timed Loop—When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register. If you use this function with the fixed-point data type, the overflow and quantization modes might impact timing.
Resources	This function requires logic resources proportional to the number of bits in x or y, whichever data type is larger. If you use this function with the fixed-point data type, the overflow and quantization modes might impact resources.