Unit Delay (FPGA Module)

LabVIEW 8.5 FPGA Module Help
August 2007

NI Part Number:
371599C-01

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Delays the input value for one cycle.

	initialize, when TRUE, returns initial condition as the output. The VI initializes automatically when it first runs in a VI.
	initial condition is the data point the VI returns the first time you call it or when initialize is TRUE.
	input is the data point the VI processes.
	output returns the delayed input value. output[n] = input[n – 1] where output[n] is the value of output on the nth call to the VI after initialization and output[0] = initial condition.