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Zero-Order Hold (FPGA Module)

LabVIEW 8.5 FPGA Module Help
August 2007

NI Part Number:
371599C-01

»View Product Info

Samples an input signal and holds it for a specified number of calls to the VI. The larger data type you wire to input or initial condition determines the polymorphic instance LabVIEW uses.

Use the pull-down menu to select an instance of this VI.

Zero-Order Hold (I16)

initialize, when TRUE, returns initial condition as the output. The VI initializes automatically when it first runs in a VI.
input is the data point the VI processes. During the hold time, the VI ignores new input values.
hold time in cycles determines the number of calls to the VI between updates to output.
output returns the zero-order hold signal. output is a sampled version of input with a sample interval of hold time in cycles.

Zero-Order Hold (I8)

initialize, when TRUE, returns initial condition as the output. The VI initializes automatically when it first runs in a VI.
input is the data point the VI processes. During the hold time, the VI ignores new input values.
hold time in cycles determines the number of calls to the VI between updates to output.
output returns the zero-order hold signal. output is a sampled version of input with a sample interval of hold time in cycles.

Zero-Order Hold (I32)

initialize, when TRUE, returns initial condition as the output. The VI initializes automatically when it first runs in a VI.
input is the data point the VI processes. During the hold time, the VI ignores new input values.
hold time in cycles determines the number of calls to the VI between updates to output.
output returns the zero-order hold signal. output is a sampled version of input with a sample interval of hold time in cycles.

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