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The fixed-point data type provides some of the flexibility of the floating-point data type but also maintains the size and speed advantages of integer arithmetic. By default, each operation on the fixed-point data type generates a fixed-point result that is large enough to hold all possible output values specified by the input types.

Note  FIFOs, memory, FPGA Math & Analysis VIs, and some functions do not support the fixed-point data type.

Caution  If you wire a fixed-point number to an integer, you might lose significant fractional bits.

Setting the Desired Range

Use the Desired Range options on the Properties dialog box to increase or decrease the resources a function uses. Right-click a numeric constant, control, indicator, or function that accepts fixed-point data and select Properties from the shortcut menu to display the Properties dialog box. When you set the range on inputs, the FPGA Module propagates the range throughout the block diagram. The propagation reduces resources when possible. The FPGA Module does not propagate through subVIs, so coercion dots appear on the inputs of subVIs if the range is different than the range being propagated.

Note  If you set the Desired Range in places other than the inputs, the VI might require additional hardware resources.

Selecting an Overflow and Quantization Mode

Functions that support the fixed-point data type include modes to handle the overflow and quantization. Use the Properties dialog box for the function to select the overflow and quantization modes. Right-click a function and select Properties from the shortcut menu to display the Properties dialog box.

Refer to the Numeric Data topic for information about each of the overflow modes. The overflow modes affect the logic generated within the FPGA as follows:

• Saturate—Requires additional hardware resources to determine if the input value is within the desired range of the output type. Saturate is the default overflow mode. If you specify a desired range other than the default minimum and maximum, the Saturate mode performs a full comparison between the desired range and input value, which might require additional clock cycles to complete. If you do not specify a desired range, the Saturate mode checks all bits above the most significant bit of the output type to ensure the output did not overflow.
• Wrap—Does not require additional hardware resources.

Refer to the Numeric Data topic for information about each of the quantization modes. Each of the quantization modes affect the logic generated within the FPGA as follows:

• Truncate—Removes fractional bit and therefore does not require any additional hardware resources. However, this mode produces the largest mean error for most data streams. This mode is the default for integer operations.
• Round-Half-Up (Asymmetric)—Adds the least significant bit and therefore requires an adder that is the width of the output type.
• Round-Half-Even—Requires the most hardware resources and has the slowest timing of the three rounding modes. However, this mode returns the most statistically correct results for most data streams and is therefore the default rounding mode for the fixed-point data type. Although this mode requires only a modest amount of additional hardware compared to the Round-Half-Up (Asymmetric) mode, the length of the longest combinatorial path is longer, which reduces the maximum clock frequency for the path.

Note  If you select the Saturate, Round-Half-Up (Asymmetric), or Round-Half-Even modes and the output can handle the overflow or quantization, the operation does not require additional hardware resources. If a coercion dot does not appear on the block diagram, the output can handle the overflow or quantization without additional hardware resources.