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Inputs and outputs (I/O) on FPGA targets allow you to connect the FPGA target to other devices. FPGA I/O resources are fixed elements of the FPGA targets that you use to transfer data among the different parts of the system. On some FPGA targets, FPGA I/O resources correspond to lines on front panel connectors, PXI backplanes, or RTSI connectors. On other FPGA targets, FPGA I/O resources are nodes inside FPGAs that connect the part of the FPGA designed by National Instruments with the part of the FPGA you design. Each FPGA I/O resource has a specific type, such as digital or analog. An FPGA target might have multiple I/O resources of the same or different types. You can create FPGA I/O items, determine the I/O resources on the FPGA target that you want to use, and then assign unique names to the I/O resources you use.

Note  Refer to the specific FPGA target hardware documentation for information about supported features and I/O functionality on the FPGA target you use. Refer to Managing Shared Resources for information about arbitrating I/O resources.

Resources translate physical quantities to or from a digital value that you manipulate in FPGA Module software. An I/O resource has a terminal for receiving or generating a physical quantity. Many I/O resources on FPGA targets have physical terminals to which you can directly connect elements of the system. For example, digital signals, sensors, actuators, and so on, on some resources are associated with terminals built into the device, such as an on-board temperature sensor.

When the FPGA VI runs on the FPGA target, it performs I/O operations in hardware. For example, if you configure an FPGA I/O Node to read a digital line, the FPGA I/O Node reads the line and returns the result to the FPGA VI. Because FPGA VIs run on the FPGA, the VI can react to the input with the speed and determinism available in the FPGA target hardware.

You can put analog and digital inputs and outputs together in the same node on the block diagram. You can use target-specific properties and methods on the FPGA I/O items with the FPGA I/O Property Node and the FPGA I/O Method Node, respectively.

Digital I/O

FPGA targets might organize digital I/O resources as individual lines or as groups of lines called ports. Some FPGA targets provide access to digital I/O resources exclusively as lines or ports. Other FPGA targets allow you to access the same physical lines both as individual lines and as ports. There are three types of digital I/O resources: those that read input, those that write output, and those that can perform both functions. Refer to the FPGA target hardware documentation for information about digital I/O support.

Digital Input Resources

You can read digital input FPGA resources with the FPGA I/O Node. Use digital input resources to monitor circuitry outside the FPGA target.

Digital Output Resources

You can write digital output FPGA resources with the FPGA I/O Node. Use digital output resources to control circuitry outside the FPGA target.

Digital Input and Output Resources

Some FPGA targets contain bidirectional, or tristate, digital I/O resources. In LabVIEW FPGA, tristate digital I/O resources are called digital input and output resources. You can read and write digital input and output resources with the FPGA I/O Node. You can use digital input and output resources to monitor and control circuitry outside the FPGA target. Tristate resources allow you to configure the I/O resource and control the direction of dataflow. Use the FPGA I/O Method Node configured with the Set Output Enable method to change the direction of dataflow. Wire a TRUE value to the Enable input to configure the tristate I/O resource as an output resource. Wire a FALSE value to the Enable input to configure the tristate I/O resource as an input resource.

Note  The default direction typically is input.

As shown in the following figure, a Digital Enable (DE) signal controls whether the line is configured for input or output. When the DE is True, the digital line is configured as an output, and the value stored in Digital Data (DD) will be driven on the digital line. When the DE is False, the digital line is configured as a high-impedance input allowing the line to be driven by an external device. Regardless of the state of the DE, the Digital Input (DI) can be monitored to observe the current state of the digital line.

In the following figure, the first frame of the Sequence structure configures DIO1 as an output resource, and the second frame writes an output value. The third frame configures DIO1 as an input resource, and the fourth frame reads an input value. If the third frame were removed, the FPGA I/O Node would not receive external input but would instead read back the same value that it wrote.

If you use an FPGA I/O Node to read a digital input and output resource, the FPGA I/O Node does not change the direction of the resource. If you use a digital input and output resource to write output, you must disable the output before you can use the same resource to read input. Use the FPGA I/O Method Node with the Set Output Enable method to disable the output line before you use an FPGA I/O Node configured with a digital input and output resource to read the state of an external signal. Otherwise, the I/O Node simply reads back the last value written by the FPGA VI.

If you use the FPGA I/O Node to write a digital input and output resource, the FPGA I/O Node both writes the data and enables the terminal for output. You also can use the FPGA I/O Method Node with the Set Output Data method to write data without enabling the output. Use the FPGA I/O Method Node with the Set Output Enable method to enable the digital terminal, which allows the data to be driven out. Use the Set Output Data method before the Set Output Enable method to specify the state of the digital input and output resource when you enable the output. For example, you might have one portion of the block diagram continuously generating an internal signal. Use the FPGA I/O Method Node with the Set Output Enable method in another portion of the block diagram to independently control when the internal signal is actually driven out to an external device.

Analog I/O

Analog Input

If the FPGA target you use includes analog input resources, you can configure an FPGA I/O Node to read an analog input value. If you configure the FPGA I/O Node to read an analog input, the FPGA I/O Node might initiate a conversion, wait for the result, then return the binary representation of the voltage as a signed integer. The analog input process and the size of the resulting data type varies by FPGA target. For many FPGA targets, you create the FPGA VI to use the binary representation for operations within the FPGA VI. You also can pass the binary representation back to the host VI and convert the binary representation to a voltage or other physical quantity if you have a transducer attached to the FPGA target analog input.

The equation you use to convert the binary representation to a physical quantity depends on the FPGA target and transducer. For example, with an NI PXI-7831R device, use the following equation to convert the binary representation to voltage: Input Voltage = (Binary Code / 32768) x 10.0V. Refer to the specific FPGA target hardware documentation for more information.

Note  Avoid executing this calculation in the FPGA VI because the FPGA does not support floating-point operations. Also, performing the calculation consumes space on the FPGA. Refer to Unsupported LabVIEW Features for more information about mathematical operations in FPGA VIs.

Analog Output

If the FPGA target you use includes analog output resources, you can configure an FPGA I/O Node to write an analog output value. If you configure the FPGA I/O Node to write an analog output, the FPGA I/O Node writes the binary representation of the voltage to the digital-to-analog converter (DAC), which sets the analog output voltage. The size of the data type varies by FPGA target. You can generate voltage information from two sources—the host VI or the FPGA VI. Typically the host VI converts the voltage to an appropriate binary representation before writing the value to the FPGA VI. If the FPGA VI determines the voltage, typically the FPGA VI performs the calculations using the appropriate binary representations. In both cases, the DAC produces a voltage that corresponds to the binary representation.

The equation you use to convert a voltage to a binary representation depends on the specific FPGA target. For example, with an NI PXI-7831R device, use the following equation to convert the voltage to the binary representation: Binary Code = (Output Voltage x 32768) / 10.0V. Refer to the specific FPGA target hardware documentation for more information.

Note  Avoid executing this calculation in the FPGA VI because the FPGA does not support floating-point operations. Also, performing this type of calculation on the FPGA uses additional space. Refer to Unsupported LabVIEW Features for more information about mathematical operations in FPGA VIs.