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To transfer data between the FPGA VI and the host VI programmatically, you can use programmatic front panel communication or Direct Memory Access (DMA). Use programmatic front panel communication for small, frequent data transfers and DMA for streaming large amounts of data at a time. The following table summarizes the characteristics of DMA and programmatic front panel communication.

Data Transfer Method	Throughput	Call Overhead	Host CPU Usage	Common Use
Programmatic Front Panel Communication	Lower	Lower	Higher	Control, Simulation
Direct Memory Access	Higher	Higher	Lower	Datalogging

If you are not sure whether to use programmatic front panel communication or direct memory access communication, try using programmatic front panel communication first. If you find that programmatic front panel communication cannot meet the throughput requirements, switch to DMA communication.

Programmatic Front Panel Communication

When you need to transfer single data points as quickly as possible, such as when transferring data for control or simulation purposes, you can use the Read/Write Control function in the host VI to access the front panel controls and indicators of the FPGA VI, as shown in the figure below.

An advantage of programmatic front panel communication relative to DMA is its low call overhead. Although you cannot attain high throughput with programmatic front panel communication, each call to the Read/Write Control function initiates data transfer with minimal delay. Therefore, programmatic front panel communication is ideal for small, frequent data transfers.

Direct Memory Access

When you do not need to transfer each data point immediately, such as when transferring data from the FPGA to the host computer for datalogging purposes, you can wait for a large amount of data to accumulate and use a DMA FIFO to transfer the data efficiently.

Note  Support of DMA FIFOs varies by FPGA target. Refer to the specific FPGA target hardware documentation for more information.

An advantage of DMA is that the host computer processor can perform calculations while the FPGA target transfers data to the host computer memory. LabVIEW performs DMA transfers through bus mastering. FPGA targets that support DMA FIFOs can master the PCI bus to directly access memory on the host computer without involving the host computer processor.

A disadvantage of DMA FIFOs is the overhead associated with each data transfer. It takes longer to initiate a data transfer using the DMA FIFO than it does using the Read/Write Control function. Therefore, DMA FIFOs make more sense for transferring large amounts of data at a time.

A DMA FIFO allocates memory on both the host computer and the FPGA target, yet acts as a single FIFO. The FPGA VI writes to the FIFO one element at a time with the FIFO Write function or reads from the FIFO one element at a time with the FIFO Read function. The host VI reads from or writes to the FIFO one or more elements at a time with the Invoke Method function.

LabVIEW uses a DMA Engine to transfer DMA FIFO data between the FPGA and the host computer. The DMA Engine includes driver software and hardware logic. When the DMA Engine runs, it automatically transfers data between the DMA FIFO memory on the FPGA and the DMA FIFO memory on the host computer so they act as one FIFO array.

Note  DMA FIFOs support the U32 integer data type. If you want to transfer a different data type, convert the data type to U32, transfer it, and then reconstitute the data in the host VI.

Specifying the depth of a DMA FIFO

When you create a DMA FIFO, you specify the size, or depth, of the FIFO buffer on the FPGA. You also can specify the size of the FIFO buffer on the host computer by using the Invoke Method function in a host VI to invoke the Configure method. If you do not specify the size of the host computer part of the FIFO in the host VI, the host computer part size defaults to twice the size of the FPGA part of the FIFO. Make sure the host computer and FPGA parts of the FIFO are large enough so that they do not fill in the case of the longest expected delay in the host VI. For example, PCI bus traffic can cause delays in automatic transfers from the FPGA target to the host. The purpose of a FIFO buffer is to accommodate jitter, so the longer the delays you expect, the more depth you need.

Consider the following situations when you specify the depth of the DMA FIFO:

• FIFO depth is too small—When a large transfer delay occurs, the DMA FIFO may fill to capacity. The Timed Out? output of the FIFO Write function returns TRUE to indicate that the FIFO is full. When the FIFO is full, new values do not replace stored values, resulting in data loss.
• FIFO depth is too large—If the FPGA part of the DMA FIFO is too large, other functions cannot use the unused memory dedicated to the FIFO. If the host part of the FIFO is too large, other programs on the host computer cannot use the unused memory in the DMA FIFO.