Reducing Combinatorial Paths in FPGA VIs (FPGA Module)
A combinatorial path is the path through logic between the output of a register and the input of another register on an FPGA. A register stores data on an FPGA and updates the data on the rising edge of a clock. Long combinatorial paths take more time to execute and limit the maximum clock rate of the clock domain.
Long combinatorial paths are typically a problem in single-cycle Timed Loops because the logic between the input register and the output register must execute within one period of the clock rate you specify. In the single-cycle Timed Loop, registers within and between components are removed, increasing the length of the combinatorial path between registers. If the code in a combinatorial path does not execute within a clock cycle, LabVIEW returns a timing violation in the Compilation Failure dialog box.
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Note Deeply nested Case structures also can cause LabVIEW to return a timing violation in the Compilation Failure dialog box. |
To reduce the length of a combinatorial path, first simplify the logic as much as possible. Once you have reduced the logic to its simplest form, you can further reduce the length of a combinatorial path by dividing the logic into discrete steps and pipelining your design.
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