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A register is a group of flip-flops that stores a bit pattern. A flip-flop is a circuit capable of two stable states and thus represents a single bit. A register on the FPGA has a clock input, input data, and output data. Every clock cycle, the input data is latched, stored internally, and the output data is updated to match the internally stored data. FPGA VIs use registers to perform the following functions.

• Holding state between iterations of a loop
• I/O synchronization
• Handshaking data between clock domains
• Pipelining
• Communicating with a host VI

Note  Registers are a low-level FPGA implementation concept. You do not need to understand registers to use the LabVIEW FPGA Module, but understanding registers can help you build more efficient FPGA VIs.

Timing Considerations

Because registers update every clock cycle, the time it takes a signal to travel from one register to the next, known as propagation delay, must not exceed the clock period. Propagation delay consists of two components, logic delay and wiring delay. Logic delay, which is a function of the number and type of logic gates the signal traverses, often represents the most significant component of propagation delay. Wiring delay, which is a function of the length of the wire path the signal traverses, is generally small, because the FPGA compiler attempts to cluster the components of a combinatorial path as tightly as possible on the FPGA. However, as the FPGA VI approaches the size limits of the FPGA, the physical separation between functions increases and wiring delay can become a significant component of the total propagation delay between two registers. The FPGA compiler returns a timing error if the propagation delay between any two registers exceeds the FPGA clock period.

Note  The actual logic delay for a given function varies by target. The actual wiring delay varies each time you compile an FPGA VI.

The LabVIEW FPGA Module is designed to produce circuits that can run at a clock rate of at least 40 MHz outside the single-cycle Timed Loop, which corresponds to a clock period of 25 nanoseconds. To prevent the propagation delay between two registers from exceeding 25 nanoseconds, most LabVIEW functions include an output register and thus require a full clock cycle to execute. If the propagation delay between two registers exceeds 25 nanoseconds, the FPGA VI cannot compile at the 40 MHz default clock rate.

For example, suppose function A requires a 6 nanosecond logic delay and function B requires a 14 nanosecond logic delay. If you wire functions A and B in sequence without a register between them, the total logic delay is 20 nanoseconds, which leaves 5 nanoseconds for wiring delay if you want the functions to compile at the 40 MHz default clock rate. Depending on how the FPGA compiler routes the wires between the functions, the wiring delay might or might not exceed 5 nanoseconds, as shown in Scenarios 1 and 2 below.

In Scenario 3 below, there is a register between the two functions, which results in two separate propagation delays, each of which can easily compile at 40 MHz, even if the wiring delay is long.

The LabVIEW FPGA Module includes internal registers only in functions that require logic. The FPGA compiler places registers at regular intervals between the levels of logic in a function to break up the logic into portions that can execute at the default FPGA clock rate. When a function that includes internal registers runs on the FPGA, the function takes as many FPGA clock cycles to execute as the number of registers in the function.

When you need logic to execute in fewer clock cycles, you can use the single-cycle Timed Loop. When you place a function inside a single-cycle Timed Loop, the compiler does not include an output register for the function so that the single-cycle Timed Loop can execute within one clock cycle. If the propagation delay within a single-cycle Timed Loop exceeds the clock period, the Compilation Failure Dialog Box tells you which single-cycle Timed Loop failed to meet timing requirements. In some cases, you can reduce the length of a combinatorial path by using Feedback Nodes or shift registers to implement a pipelined design.

Note  A shift register is implemented using an internal FPGA register.

Resource Considerations

Every FPGA target contains a limited number of flip-flops. Because registers use flip-flops, the number and type of registers used by an FPGA VI can determine whether the FPGA VI fits on the FPGA target. In general, the number of flip-flops used by a register corresponds to the width of the data type. For example, a Boolean register needs only one flip-flop to store data while an I64 register requires 64 flip-flops to store data.

Note  Registers that store front panel control and indicator data require more flip-flops than internal registers, to facilitate communication with the host VI. To conserve space on the FPGA, consider limiting front panel controls and indicators.