Opening a Reference to an FPGA VI
Communication with an FPGA VI Running on a Development Computer
Using Multiple FPGA VI References for the Same Target
Reading FPGA VI Indicators
Writing to FPGA VI Controls
Reading DMA FIFOs from Host VIs
Writing to DMA FIFOs from Host VIs
Using SubVIs in Host VIs
Synchronizing FPGA VIs and Host VIs Using Interrupts
Forcing an FPGA VI to Download to an FPGA Target
Stopping, Aborting, and Resetting FPGA VIs
Close FPGA VI Reference
Invoke Method
Open FPGA VI Reference
Read/Write Control
Advanced Function