Advanced Palette Details (FPGA Module)

LabVIEW 8.6 FPGA Module Help
June 2008

NI Part Number:
371599D-01

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This topic contains FPGA-specific information about the objects on the Advanced palette.

Note The information in this topic is subject to change with each version of the LabVIEW FPGA Module.

HDL Interface Node

Single-Cycle Timed Loop	You can use the HDL Interface Node inside a single-cycle Timed Loop. However, you must ensure that the HDL code you use can compile at the clock rate of the single-cycle Timed Loop.
Usage	The HDL Interface Node is intended only for experienced HDL programmers.
Timing	Execution time depends on the HDL code you use in the HDL Interface Node.
Resources	Resource usage depends on the HDL code you use in the HDL Interface Node.

Note Refer to Importing HDL Code into FPGA VIs for more information about the HDL Interface Node.