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Owning Palette: Discrete Linear Systems VIs

Installed With: FPGA Module

Integrates a discrete input signal using forward Euler integration. The VI assumes that the integration interval (dt) is normalized to 1. The data type you wire to input determines output data type, where output word length is equal to input word length + 16 bits.

The maximum input word length is 32 bits.

Details  

	reset, when TRUE, returns initial condition as the output. The VI initializes automatically when it first runs in a VI.
	input is the data point the VI processes.
	initial condition is the data point the VI returns the first time you call it or when reset is TRUE.
	output returns the forward integration result. output[n] = input[n – 1] + output[n – 1] where output[n] is the value of output on the nth call to the VI and output[0] = initial condition.

Discrete Normalized Integrator Details

If the output exceeds the range of the output data type, the result saturates, returning the maximum numeric value representable by the output and its data type with the same sign as the actual result.

The Discrete Normalized Integrator VI assumes a sampling interval (dt) of 1 and implements a discrete accumulator. To use the VI as a stand-alone integrator, multiply the input or output by dt externally or in a host VI. To implement a transfer function from several integrators, you must take the sampling interval into account during the transfer function design phase.