Owning Palette: FPGA Module VIs and Functions
Installed With: FPGA Module. This topic might not match its corresponding palette in LabVIEW depending on your operating system, licensed product(s), and target.
Use the FPGA Math & Analysis VIs to perform math, analysis, and control operations in FPGA VIs.
![]() | Note This palette is specific to FPGA targets. |
Refer to IPNet for additional FPGA functions and example IP.
| Palette Object | Description |
|---|---|
| Analog Period Measurement | Calculates the period of an evenly sampled periodic signal using threshold crossing detection. |
| Butterworth Filter | Filters one or more input signals using a lowpass or highpass IIR Butterworth filter. |
| DC and RMS Measurements | Calculates the DC (Mean) and/or RMS values of an input signal. You also can use this VI to calculate the intermediate Sum, Mean Square, or Square Sum values in order to save FPGA resources. |
| FFT | Computes the Fast Fourier Transform (FFT) point by point. |
| Look-Up Table 1D | Provides a general-purpose block of initialized memory. Use look-up tables to store waveforms for signal generation, to model nonlinear systems, and for arithmetic computations. If you use the Look-Up Table 1D Express VI in a single-cycle Timed Loop, wire the outputs directly to Feedback Nodes. The Look-Up Table 1D Express VI takes an entire clock cycle to execute in a single-cycle Timed Loop. |
| Notch Filter | Attenuates a specific frequency band in one or more input signals using a second order IIR notch filter. |
| Rational Resampler | Provides a rational resampling filter, which updates the input sample rate by an L/M factor where L is an interpolation factor and M is a decimation factor. |
| Scaled Window | Minimizes spectral leakage associated with truncated waveforms. |
| Subpalette | Description |
|---|---|
| Control VIs | Use the Control VIs in FPGA VIs to create control applications for FPGA targets. |
| Generation VIs | Use the Generation VIs in FPGA VIs to generate signals. |
| Utilities VIs | Use the Utilities VIs in FPGA VIs to perform various tasks such as detecting state changes of Boolean inputs, detecting zero crossings, delaying the input value, limiting the valid range of a signal, and performing linear interpolation. |