You are here: NI Home > Support > Product Reference > Manuals > LabVIEW 8.6 FPGA Module Help

Owning Palette: FPGA Math & Analysis VIs

Installed With: FPGA Module

Attenuates a specific frequency band in one or more input signals using a second order IIR notch filter.

Details  

Dialog Box Options

Block Diagram Inputs

Block Diagram Outputs

Dialog Box Options

Parameter	Description
Filter Specifications	Contains the following options: Expected sample rate (S/s)—Specifies the sample rate of the input signal. This Express VI uses the rate you specify to calculate the normalized notch frequency, which is Notch frequency/Expected sample rate. Caution  The actual sample rate is specified elsewhere in the application. If the sample rate changes, you must change the Expected sample rate in this VI. Otherwise, this VI might not behave as expected. Notch frequency (Hz)—Specifies the center frequency for the notch filter to attenuate. Specify quality—Allows you to configure the Q factor of the notch filter. Q factor—Specifies the quality factor of the notch filter. This option is available only when you select Specify quality. Specify bandwidth—Allows you to configure the Notch width (Hz) of the notch filter. Notch width (Hz)—Specifies the 3-dB bandwidth of the filter, which is the frequency range for which the filter attenuates the signal energy by a factor of two or more. This option is available only when you select Specify bandwidth.
Output Data Type	Contains the following options: Avoid overflow—Specifies that the word length and integer word length of the output data type are large enough to ensure that the filter output does not overflow. Same as input—Specifies that the output data type is the same as the input data type. The output will saturate if the output range is exceeded during signal transients. Overflow will not occur with a steady-state sinusoidal input.
Implementation	Contains the following options: Number of channels—Specifies the number of channels of input data to process. The calling VI must supply a sequential channel scan to input data on successive calls to this Express VI. The channel order must be fixed. Show reset terminal—Specifies whether this Express VI includes a reset input on the block diagram to reset the Express VI at run time. You can save resources on the FPGA if you do not place a checkmark in the Show reset terminal checkbox. Show configuration terminal—Specifies whether the VI provides an input terminal to enable loading new filter coefficients while the VI runs. When you configure the VI for a single channel, this input terminal is called scaled coefficients. When you configure the VI for multiple channels, this input terminal is called configuration. Note  Adding a configuration terminal increases the FPGA resource usage of this Express VI.
Filter Response	Displays the actual magnitude response of the filter.

Block Diagram Inputs

Parameter	Description
reset	Resets the filter states of the input data channel to zero if TRUE. Resetting the filter states does not reset the filter coefficients. This input is available only when you place a checkmark in the Show reset terminal checkbox on the configuration dialog box.
input data	Specifies the input signal to filter. input data is a fixed-point number or integer with a maximum word length of 32 bits.
scaled coefficients	Specifies single-channel filter coefficients to load at run time. Scaled coefficients is a fixed-size array of three 32-bit signed integers.This parameter is available only when you configure the VI for single-channel input and place a checkmark in the Show configuration terminal checkbox on the configuration dialog box.
configuration	Specifies the scaled coefficients to load at run time for the channel index you specify using the channel index element of this cluster. This Express VI continues to use either the default coefficients or the last coefficients you specified for the channel until you specify new coefficients. This parameter is available only when you configure the VI for multi-channel input and place a checkmark in the Show configuration terminal checkbox on the configuration dialog box.

Block Diagram Outputs

Parameter	Description
output data	Returns the filtered signal corresponding to the input data channel.

Notch Filter Details

You can configure the sharpness of the notch by specifying either the Notch width or the Q factor of the filter. To use Notch width, select Specify bandwidth in the Filter Specifications section of the configuration dialog box. To use Q factor, select Specify quality in the Filter Specifications section of the configuration dialog box.

Q factor and Notch width are related by the following equation:

Q factor = Notch frequency/Notch width.

Notch frequency and Notch width or Q factor are constrained such that the upper end of the attenuated frequency band is less than half of the Expected sample rate (S/s) (Nyquist frequency) and the lower end of the attenuated frequency range is greater than zero (DC).

Refer to the Developer Zone for more information about the accuracy of the FPGA Math and Analysis VIs.