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Owning Palette: FPGA Math & Analysis VIs

Installed With: FPGA Module

Provides a rational resampling filter, which updates the input sample rate by an L/M factor where L is an interpolation factor and M is a decimation factor. Rational resampling is the process of converting the sample rate of a signal to another sample rate that differs from the original sample rate by a rational factor of L/M, where both L and M are integer values. When L=1,M>1, the resampling is an integer decimation, and when L>1,M=1, the resampling is an integer interpolation.Rational resampling is useful for interfacing with digital signal processing (DSP) systems that operate at different sample rates. By choosing L and M properly, you can approximate any desired sample rate change ratio.

Details  

Dialog Box Options

Block Diagram Inputs

Block Diagram Outputs

Dialog Box Options

Parameter	Description
Filter Parameters	Contains the following options: L—Specifies the interpolation factor. M—Specifies the decimation factor. Note  L and M must never be equal. Stopband attenuation—Specifies the attenuation above where the gain versus frequency has finished its rapid falloff. The default is 80 dB. Input sample rate—Specifies the sample rate of each input channel. The Input sample rate, combined with L and M, determines the Output sample rate. Output sample rate—Indicates the calculated average rate at which the Express VI returns valid output data for each channel.
Implementation	Contains the following options: Number of channels—Specifies the number of source channels that this Express VI handles. Adapt to source—Specifies whether the Express VI decides the output data type. Do not place a checkmark in this checkbox if you want to use the Word length control to determine the output data type. Word length—Specifies any output word length in the range of [1, 32]. This control is available only if you did not place a checkmark in the Adapt to source checkbox. Integer word length—Indicates the output integer word length that the Express VI calculates. Show reset terminal—Specifies whether this Express VI includes a reset input on the block diagram to reset the Express VI at run time. You can save resources on the FPGA if you do not place a checkmark in the Show reset terminal checkbox.
Filter Response	Displays the actual magnitude response of the filter.
Execution	Contains the following options: Outside single-cycle Timed Loop—Select this option when you want to use this Express VI outside of a single-cycle Timed Loop. Outside single-cycle Timed Loop is disabled when L/M is greater than 1. Inside single-cycle Timed Loop—Select this option when you want to use this Express VI inside a single-cycle Timed Loop. Selecting Inside single-cycle Timed Loop enables the Throughput indicator. When you execute this Express VI inside the single-cycle Timed Loop, the Express VI provides four handshaking signals you can use to schedule the timing of data. This option is useful if you want to achieve higher throughput using a rational resampling filter. Throughput—Displays the minimum cycles between two successive valid input data.

Block Diagram Inputs

Parameter	Description
reset	Resets the state of the internal resampling filter. Outside the single-cycle Timed Loop, the Express VI restarts on the same call that reset is TRUE. Inside the single-cycle Timed Loop, the Express VI restarts on the first call that reset is deasserted after reset is TRUE. Additionally, the handshaking signals behave as follows during the cycles where reset is asserted: input valid is ignored. ready for output is ignored. output valid is FALSE. ready for input is FALSE, which handles cases where reset is held TRUE for a long time. The Express VI is not ready for inputs when reset is asserted.
input data	Specifies the data you want to filter.
input valid	Specifies that the next data point has arrived for processing. This terminal is available only when you have selected Inside single-cycle Timed Loop. The input valid terminal is required inside the single-cycle Timed Loop.
ready for output	Specifies that the rest of the block diagram is ready for the Express VI to output a new value. The default is TRUE. This terminal is available only when you have selected Inside single-cycle Timed Loop. Note  If this signal is FALSE on a given cycle, the output valid signal is also FALSE for that cycle.

Block Diagram Outputs

Parameter	Description
channel index	Indicates the index of the channel corresponding to the last valid output data.
output data	Returns the filtered data.
output valid	Indicates that the Express VI has updated the current data point and the data point is ready to be used by downstream LabVIEW objects.
ready for input	Indicates that the Express VI is ready to accept new input data. This terminal is available only when you are using the Express VI inside the single-cycle Timed Loop. Note  If this signal is FALSE on a given cycle, the Express VI does not accept data on the following cycle. If input valid is TRUE on the following cycle, the input data is lost.

Rational Resampler Details

Refer to Scheduling Timing Using Handshaking Signals for information about using the handshaking signals available for this Express VI.