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Owning Palette: Timed Structures

Installed With: FPGA Module

Starts disabling an FPGA clock to protect circuitry dependent on a periodic clock. Use this VI to disable the clock prior to glitches or before the clock signal becomes unavailable. Clocks that support and require enabling and disabling at run time begin disabled after you download or reset the FPGA VI. When you reenable the clock using the Start Enabling FPGA Clock VI, the state of all registers and memory using the disabled clock is the same as the last cycle before the clock was disabled.

You must include the Start Disabling FPGA Clock VI outside of the single-cycle Timed Loop that is using the clock you are disabling.

Details  

	FPGA Clock to Disable specifies the clock to disable. The clock you specify must support disabling at run time. To configure a clock to support disabling, place a checkmark in the Supports and Requires Runtime Enable/Disable checkbox in the FPGA Base Clock Properties dialog box.
	error in describes error conditions that occur before this VI or function runs. The default is no error. If an error occurred before this VI or function runs, the VI or function passes the error in value to error out. This VI or function runs normally only if no error occurred before this VI or function runs. If an error occurs while this VI or function runs, it runs normally and sets its own error status in error out. Use error in and error out to check errors and to specify execution order by wiring error out from one node to error in of the next node. status is TRUE (X) if an error occurred before this VI or function ran or FALSE (checkmark) to indicate a warning or that no error occurred before this VI or function ran. The default is FALSE. code is the error or warning code. The default is 0. If status is TRUE, code is a nonzero error code. If status is FALSE, code is 0 or a warning code. source specifies the origin of the error or warning and is, in most cases, the name of the VI or function that produced the error or warning. The default is an empty string.
	error out contains error information that corresponds to the error code. Right-click the error out front panel indicator and select Explain Error or Explain Warning from the shortcut menu for more information about the error or warning. status is TRUE (X) if an error occurred or FALSE (checkmark) to indicate a warning or that no error occurred. code is the error or warning code. If status is TRUE, code is a nonzero error code. If status is FALSE, code is 0 or a warning code. source describes the origin of the error or warning and is, in most cases, the name of the VI or function that produced the error or warning.

Start Disabling FPGA Clock Details

Single-Cycle Timed Loop	Supported.
Usage	You must configure the FPGA VI to execute the Start Disabling FPGA Clock and Start Enabling FPGA Clock VIs at different times.The Start Disabling FPGA Clock VI has no effect when you run an FPGA VI on a development computer or use the VI on a non-FPGA target.
Timing	A short delay exists before the clock is actually disabled because the disable must go through one register in the clock domain where the Start Disabling FPGA Clock VI is running and two registers in the clock domain you want to disable.
Resources	This VI consumes minimal logic resources on the FPGA.