Unit Delay VI

LabVIEW 8.6 FPGA Module Help
June 2008

NI Part Number:
371599D-01

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Owning Palette: Discrete Linear Systems VIs

Installed With: FPGA Module

Delays the input value for one cycle. The data type you wire to input determines the output data type.

The maximum input word length is 32 bits.

	reset, when TRUE, returns initial condition as the output. The VI initializes automatically when it first runs in a VI.
	input is the data point the VI processes.
	initial condition is the data point the VI returns the first time you call it or when reset is TRUE.
	output returns the delayed input value. output[n] = input[n – 1] where output[n] is the value of output on the nth call to the VI after initialization and output[0] = initial condition.