Zero-Order Hold VI

LabVIEW 8.6 FPGA Module Help
June 2008

NI Part Number:
371599D-01

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Owning Palette: Discrete Linear Systems VIs

Installed With: FPGA Module

Samples an input signal and holds it for a specified number of calls to the VI. The data type you wire to input determines the output data type.

The maximum input word length is 32 bits.

	reset, when TRUE, returns initial condition as the output. The VI initializes automatically when it first runs in a VI.
	input is the data point the VI processes. During the hold time, the VI ignores new input values.
	hold time in cycles determines the number of calls to the VI between updates to output.
	output returns the zero-order hold signal. output is a sampled version of input with a sample interval of hold time in cycles.

Zero-Order Hold VI

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