Compilation Failure Dialog Box
Installed With: FPGA Module
The Compilation Failure dialog box appears when a compilation fails. This failure can indicate that the VI is too large for the FPGA or that the VI contains a timing violation. Refer to Optimizing FPGA VIs for Speed and Size for information about optimizing the VI. This failure also can indicate an error in the LabVIEW FPGA Module code generation or in the FPGA Module compiler. Report the error to NI technical support.
This dialog box includes the following tabs:
- Summary—Includes the following categories of information:
- Status—Lists possible causes for the failure, which can include the following:
- Compilation failed due to resource overmapping—The current VI requires more resources than are available. Follow the recommendations in the Compilation Failure dialog box to reduce resource use.
- Compilation failed due to timing violations—A clock rate used is too fast for part(s) of this VI. If the FPGA VI contains multiple violations in the same clock domain, LabVIEW reports only one violation for the clock domain in the Compilation Failure dialog box. In some cases, if you fix the reported violation, you also resolve the other violations. However, if violations still exist, LabVIEW reports the next violation in the clock domain when you recompile.
LabVIEW cannot always detect the location of the violation. If LabVIEW can detect the location of the violation and the violation occurs within a single-cycle Timed Loop, the Compilation Failure dialog box returns the loop name, which you set in the Loop Name field of the Configure Timed Loop dialog box.
Consider the following recommendations to resolve timing violations:- Change the code with timing violations—Refer to Optimizing FPGA VIs for Speed and Size for information about optimization techniques.
- Reduce clock rates if possible—Select a lower clock rate and recompile.
- Recompile—The compilation process does not produce the same results each time you compile an FPGA VI because the process maps the block diagram to the FPGA non-deterministically for each compilation. In the Compilation Summary, if the Achieved Rate is near the Requested Rate, recompile the VI. However, if the Achieved Rate is not near the Requested Rate, recompiling does not make a difference.
- Compilation failure—The compilation has failed. Try to find the smallest VI that reproduces this error and contact National Instruments technical support.
- Device Utilization Summary—Might contain the following information:
- Number of SLICES—Specifies how much of the FPGA logic the compiled FPGA VI uses.
- Number of MULT18X18s—Specifies how many built-in or hardware multipliers the compiled FPGA VI uses.
- Number of RAMB16s—Specifies how much RAM the compiled FPGA VI uses.
- Clock Rates—Might contain the following information:
- Requested Rate—Displays the clock rate at which the compiled FPGA VI runs.
Note The Requested Rate is the configured clock rate adjusted for jitter and accuracy. - Achieved Rate—Displays the compile rate for the FPGA VI.
- Requested Rate—Displays the clock rate at which the compiled FPGA VI runs.
- Status—Lists possible causes for the failure, which can include the following:
- Advanced—Includes the xflow.log and .twr files. The xflow.log file includes Xilinx-specific details about the compilation process. If you are familiar with Xilinx tools, you might be able to use this file to troubleshoot compilation failures. The .twr file is a trace report that provides detailed timing information.
This dialog box also includes the following component:
- Recompile—Forces a new compile to start. If the previous compile produced an error and you have fixed the cause of the error, click the Recompile button to force a new compile.