Defining the IP Interface (FPGA Module)
To add IP as a component-level IP (CLIP) item in a LabVIEW project, the IP must have an accompanying declaration XML file to define the I/O for the FPGA Module. The declaration XML file describes the elements of the IP, and the FPGA Module uses the file to add the IP to a LabVIEW project. If you are not familiar with XML, refer to www.w3.org/XML for more information.
Creating a Declaration File
The first line of the declaration file includes the XML version, and all tags inside the file must be enclosed in <CLIPDeclaration> tags as shown below:
<?xml version="1.0"?>
<CLIPDeclaration Name="My VHDL IP">
<!-- Insert tags here -->
</CLIPDeclaration>
The following table defines the XML tags you can use in the declaration file.
| Tag | Required? | Parent Tag | Number of Tags within Parent Tag | Description |
| CLIPDeclaration | Yes | — | — | All CLIP definitions must be contained within this tag. Name is a required attribute that defines the name of the CLIP that LabVIEW displays. |
| FormatVersion | Yes | CLIPDeclaration | 1 | Defines which version of the CLIP tags were used to create the declaration XML file. The tags defined in this table use version 1.0, so you must set this tag to 1.0. |
| HDLName | Yes | CLIPDeclaration | 1 | Specifies the top-level HDL entity of the top-level VHDL file. |
| InterfaceList | Yes | CLIPDeclaration | 1 | Contains multiple interface definitions. You cannot nest interface lists, and you can define only one interface list. |
| Interface | Yes | InterfaceList | 1 or more | Defines all the I/O and clocks available to or from the CLIP. You cannot nest interfaces. Name is a required attribute. |
| InterfaceType | Yes | Interface | 1 | Defines where the interface is connected in the FPGA. You can select from the following values:
|
| SignalList | Yes | Interface | 1 | Contains multiple signal definitions. You cannot nest SignalList tags. |
| Signal | Yes | SignalList | 1 or more | Defines a signal that will be available to or from the CLIP. Must contain the Name attribute, which the FPGA Module uses for display purposes. The Name attribute must only contain English letters and numbers, periods, dashes, and underscores. |
| HDLName | No | Signal | 0 or 1 | Defines the name of the I/O entity in the VHDL file. The default is the Name attribute you declare in the Signal tag. |
| DataType | Yes | Signal | 1 | Defines the data type of the signal. If the signal is for a LabVIEW interface, the data type also defines how LabVIEW represents this signal. If the signal is for a socket interface, the data type must match the data type of the signal in the socket. Use one of the following child tags to define the data type:
|
| Boolean * | No | DataType or Array | 1 | Specifies that the VHDL code uses std_logic. |
| U8 * | No | DataType | 1 | Specifies that the VHDL code uses std_logic_vector(7 downto 0). |
| U16 * | No | DataType | 1 | Specifies that the VHDL code uses std_logic_vector(15 downto 0). |
| U32 * | No | DataType | 1 | Specifies that the VHDL code uses std_logic_vector(31 downto 0). |
| I8 * | No | DataType | 1 | Specifies that the VHDL code uses std_logic_vector(7 downto 0). |
| I16 * | No | DataType | 1 | Specifies that the VHDL code uses std_logic_vector(15 downto 0). |
| I32 * | No | DataType | 1 | Specifies that the VHDL code uses std_logic_vector(31 downto 0). |
| Array | No | DataType | 1 | Creates an array of the Boolean data type. You must include the Boolean tag within the Array tag. You only can use the Array tag with socketed CLIP. |
| Size | Yes | Array | 1 | Specifies the size of the array. |
| Direction | No | Signal | 0 or 1 | Indicates if the CLIP receives or sends data on the signal. You can select from the following values:
|
| SignalType | No | Signal | 0 or 1 | Indicates the type of signal. You can select from the following values:
|
| FreqInHertz | No | Signal | 1 | Defines the frequency range of the signal. The FreqInHertz tag is required if the SignalType is set to clock. |
| Max | Yes | FreqInHertz | 1 | Defines the maximum supported frequency in SI notation. The Max tag is required if you include a FreqInHertz tag. |
| Min | No | FreqInHertz | 0 or 1 | Defines the minimum supported frequency in SI notation. If you do not specify a value for Min, the Min value equals the Max value. |
| ImplementationList | Yes | CLIPDeclaration | 1 | Defines the CLIP files to include. You can include only one ImplementationList tag. |
| Path | Yes | ImplementationList | 1 or more | Defines the path or directory that contains the implementation file(s) that are required for the IP to compile. The path to a directory does not include subdirectories, so you must define subdirectories in a separate tag. The Path tag assumes either a path relative to the XML file or an absolute path. When defining a relative path to a subdirectory, use a period (.) to indicate the current working directory and a slash (/ or \) to get to the next subdirectory. For example, ./folderA/fileB.vhd points to the fileB.vhd file that is inside of the folderA directory, which is at the same hierarchical level as the XML file on disk. LabVIEW returns an error for invalid paths. LabVIEW does not return an error for a path to an empty directory unless no other file or directory tags exist in the XML file. |
* This tag does not contain a value, so you can use a forward slash in the open tag or create empty open and close tags. For example, you can use <Boolean /> or <Boolean> </Boolean> to indicate a Boolean data type.
Using a Schema to Reduce Errors
XML schema files are definition files that constrain an XML file to a certain format. You can add a schema file to most XML editing tools when writing an XML file. Use the CLIPDeclaration.xsd schema file in the labview\FPGA\CLIP\Schema directory to minimize syntax and formatting errors when you create a CLIP declaration file.
CLIP Tutorial, Part 2: Declaration XML File
You can use the following example XML declaration to implement the example DemoClipAdder.vhd file as CLIP in LabVIEW. To use this example, copy the contents to a text file, save the file as DemoClipAdder.xml, and include the file in the same directory as the DemoClipAdder.vhd file.
<?xml version="1.0" encoding="utf-8"?>
<CLIPDeclaration Name="DemoClipAdder">
<FormatVersion>1.0</FormatVersion>
<HDLName>DemoClipAdder</HDLName>
<ImplementationList>
<Path>DemoClipAdder.vhd</Path>
</ImplementationList>
<InterfaceList>
<Interface Name="DemoClipAdderIO">
<InterfaceType>LabVIEW</InterfaceType>
<SignalList>
<Signal Name="Clock">
<HDLName>clk</HDLName>
<DataType>
<Boolean />
</DataType>
<Direction>ToCLIP</Direction>
<SignalType>clock</SignalType>
<FreqInHertz>
<Max>200M</Max>
<Min>1M</Min>
</FreqInHertz>
</Signal>
<Signal Name="PortA">
<HDLName>cPortA</HDLName>
<DataType>
<I16/>
</DataType>
<Direction>ToCLIP</Direction>
<SignalType>data</SignalType>
</Signal>
<Signal Name="PortB">
<HDLName>cPortB</HDLName>
<DataType>
<I16/>
</DataType>
<Direction>ToCLIP</Direction>
<SignalType>data</SignalType>
</Signal>
<Signal Name="AdderOut">
<HDLName>cAddOut</HDLName>
<DataType>
<I16/>
</DataType>
<Direction>FromCLIP</Direction>
<SignalType>data</SignalType>
</Signal>
</SignalList>
</Interface>
<Interface Name="Reset">
<InterfaceType>Fabric</InterfaceType>
<SignalList>
<Signal Name="Reset">
<HDLName>aReset</HDLName>
<DataType>
<Boolean />
</DataType>
<Direction>ToCLIP</Direction>
<SignalType>reset</SignalType>
</Signal>
</SignalList>
</Interface>
</InterfaceList>
</CLIPDeclaration>
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