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Handshaking refers to the communication between two objects that establishes the parameters for further or continued communication. When you run the Rational Resampler, Scaled Window, or FFT Express VI inside a single-cycle Timed Loop, you can use handshaking signals to schedule the timing of data. These handshaking signals specify whether the Express VIs are ready to send and receive new data.

LabVIEW provides the following terminals as handshaking signals:

• input valid—Specifies that the next data point has arrived for processing. Wire the output valid output of the upstream Express VI to this input to transfer data from the upstream Express VI to the current Express VI.
• ready for input—Indicates whether the Express VI can accept a new data point. Use a Feedback Node to wire this output to the ready for output input of the upstream Express VI.
• output valid—Indicates that the current data point produced by the VI is updated and ready to be used by downstream LabVIEW objects. Wire this output to the input valid input of the downstream Express VI to transfer data from the current Express VI to the downstream Express VI.
• ready for output—Specifies whether the downstream Express VI can accept a new data point. Use a Feedback Node to wire the ready for input output of the downstream Express VI to this input of the current Express VI.

The ready for input output remains FALSE until the current Express VI can accept new data. When the current Express VI can accept new data, the Express VI sets ready for input to TRUE and sends this value to the ready for output input of the upstream Express VI. If the upstream Express VI has a valid data point to send to the current Express VI and ready for output is TRUE, the upstream Express VI sends an output valid value of TRUE to the input valid input of the current Express VI. The upstream Express VI also sends the data point to the current Express VI. This cycle continues until the current Express VI can no longer accept new data. The current Express VI then sets ready for input to FALSE, and the upstream Express VI stops sending data to the current Express VI on the next cycle.

The following block diagram demonstrates how to use the handshaking signals to schedule the timing of data between the Rational Resampler, Scaled Window, and FFT Express VIs. The block diagram uses FIFOs to read data from and write data to VIs outside the single-cycle Timed Loop.

In the previous block diagram, the Input FIFO passes data to the Rational Resampler Express VI. If the Input FIFO has no data to pass, the FIFO times out. LabVIEW then passes a FALSE value to the input valid input of the Rational Resampler Express VI. If the Input FIFO does not time out, LabVIEW sends a TRUE value to the input valid input of the Rational Resampler Express VI. The Express VI determines whether it can accept new data, and if it can, sends a ready for input value of TRUE to the Case structure containing the Input FIFO on the next cycle. LabVIEW reads the Input FIFO and sends the data point to the Express VI. Concurrently, the Rational Resampler VI sends data to the Scaled Window Express VI if the Scaled Window Express VI can accept new data. In turn, the Scaled Window Express VI sends data to the FFT Express VI.

The FFT Express VI sends the resulting data to the Output FIFO. If the Output FIFO times out, meaning that the current write failed and that you must retry the write, it sends a FALSE value to the ready for output input of the FFT Express VI. LabVIEW sends this same FALSE value to both Select functions. The first Select function recycles the same data so it is ready for when the Output FIFO can next accept data. The second Select function sends a TRUE value to the Case structure containing the Output FIFO, thereby querying the FIFO again to determine whether it can accept new data. When the Output FIFO can accept new data, LabVIEW writes the data point to the Output FIFO. Because the FIFO does not time out, LabVIEW sends a TRUE value to the ready for output input of the FFT Express VI. The FFT Express VI then sends an output valid value of TRUE to the Case structure containing the Output FIFO. The FFT Express VI also passes a new data point to the Output FIFO.

Timing Limitations When Using Handshaking Signals

You must consider two possible timing limitations, throughput and burstiness, when building a system that uses the handshaking signals LabVIEW provides.

Throughput

If you send data to the Rational Resampler, Scaled Window, or FFT Express VI at a higher average throughput than the Express VI can handle, you might lose some data. For example, suppose the clock rate of the FPGA is 40 MHz and the input sample rate is 200kS/s. The required system throughput is the clock rate divided by the input sample rate, or 200 cycles/sample. If the maximum throughput of the Express VI is less than 200 cycles/sample, some input data points might collect in the internal buffer of the Express VI. If this buffer is full, any additional input data points are lost.

Note  The throughput for a system is inversely proportional to the number of channels in the system. For example, if the system throughput is 200 cycles/sample and the system has four channels, the system throughput is 50 cycles/sample.

Ensure that each Express VI you use allows a throughput greater than the maximum average throughput of the system. The configuration dialog box for each Express VI indicates the maximum throughput it can allow.

Burstiness

Note  The behavior described in this section applies only for the burst mode where throughput = log2(N)/2+1).

The FFT Express VI collects all input data points over a period of N cycles, calculates the FFT for all points at once over a period of (log₂N–1)/2 cycles, and then outputs the transform over a period of N cycles. The Express VI does not input or output data while it is calculating the FFT. The Express VI therefore accepts and outputs data in bursts. Handle these bursts by creating an input FIFO to hold the data points that collect while the FFT Express VI is not accepting or outputting new data.

Ensure that the FIFO you create is large enough to hold all data points that collect during the FFT calculation time. You can roughly estimate the size of the FIFO to create by dividing the FFT calculation time by the average system throughput.

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