Optimizing FPGA VIs for Speed and Size (FPGA Module)
If you want to optimize the performance of an FPGA VI, you might be able to modify the FPGA VI to increase speed, decrease the FPGA logic utilization, or both.
The following table includes techniques you can use to optimize an FPGA VI.
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Note To understand the techniques in this table, you must be familiar with registers. |
| Optimization Technique | FPGA Speed | FPGA Size |
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Reduce combinatorial paths. |
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Use pipelining when appropriate. |
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Use parallel operations. |
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Select appropriate arbitration options. |
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Use non-reentrant subVIs. |
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Use reentrant subVIs. |
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Limit the number of front panel objects, such as arrays. |
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Use the smallest data type possible. |
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Avoid large VIs and functions, if possible. |
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Schedule timing using handshaking signals. |
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