Using VHDL Code as Component-Level IP (FPGA Module)
You must be familiar with VHDL and have basic XML knowledge to use component-level intellectual property (CLIP). Use CLIP to instantiate VHDL code with a defined interface that occupies a portion of an FPGA. Unlike the HDL Interface Node, you can use CLIP to perform the following tasks:
- Run VHDL code in parallel with LabVIEW code.
- Execute VHDL code in multiple clock domains.
- Include constraints in the compilation.
In addition, some FPGA targets support accessing hardware I/O.
Types of CLIP
Support for CLIP varies by FPGA target. Refer to the target hardware documentation for information about CLIP support. Some FPGA targets support one or both of the following types of CLIP:
- User-defined CLIP—Enables VHDL code to communicate directly with an FPGA VI.
- Socketed CLIP—Enables VHDL code to communicate directly with an FPGA VI and FPGA pins that are not exposed to the LabVIEW FPGA Module. Some FPGA targets define a fixed CLIP socket in the FPGA where you can insert socketed CLIP.
The following illustration shows the relationship between an FPGA VI and CLIP.
Adding CLIP to an FPGA Target
To add CLIP to an FPGA target, you must complete the following steps:
- Create or acquire the IP.
- Define the interface to the IP using a declaration XML file.
- Declare the CLIP in the properties of an FPGA target.
- Add a CLIP item to a LabVIEW project.
- Pass data between CLIP and an FPGA VI.
Use the topics in this book to guide you through each step. Each topic also includes part of a tutorial you can use to practice creating and using CLIP.
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