Top-Level Clock FPGA Target Properties Page
Installed With: FPGA Module
Right-click an FPGA target in the Project Explorer window and select Properties from the shortcut menu to display the FPGA Target Properties dialog box. Select Top-Level Clock from the Category list to display this page.
Use this page to set the top-level clock of the FPGA target.
A base clock is a digital signal existing in hardware that you can use as a clock for an FPGA Module application. A derived clock is a clock you create from a base clock that you can use as a clock for an FPGA Module application. The top-level clock is the global clock that the FPGA VI uses outside a single-cycle Timed Loop.
Supported top-level clocks vary according to FPGA target.
This page includes the following components:
- Default—Specifies that the top-level clock of the FPGA target is the default target base clock.
- Select Configured Clock—Allows you to select a clock other than the default FPGA target clock as the top-level clock. Select from existing clocks included with the target or derived clocks you create.
- Configured Clocks—Displays the list of available clocks you can set as the top-level FPGA target clock. You can select a clock in this list if you click the Select Configured Clock option.
Note You cannot select a clock that can be disabled as a top-level clock because the clock might prevent execution of the FPGA VI. Therefore, you cannot select an external clock as a top-level clock. You also cannot select a clock that must be enabled and disabled at run time. - Selection—Displays information about the top-level clock and if the FPGA target supports the clock you want to use.