Using FIFOs in FPGA VIs (FPGA Module)
Complete the following steps to read from or write to a FIFO in an FPGA VI.
- Create a new project or open an existing project.
- Add an FPGA target to the project.
- Right-click the FPGA target and select New»VI from the shortcut menu to add an FPGA VI to the project. You also can open an existing FPGA VI.
- Create an FPGA FIFO in the project or using the VI-Scoped FIFO Configuration node.
- Place a FIFO Read or FIFO Write function on the block diagram of the FPGA VI.FIFO Read FIFO Write
- Right-click the FIFO Read or FIFO Write function and select Select FIFO»x from the shortcut menu, where x is the name of the FPGA FIFO item in the Project Explorer window or the VI-scoped FIFO item on the block diagram. LabVIEW prepends VI:: to the name of VI-scoped FIFO items.
You also can click the FPGA FIFO item in the Project Explorer window and drag it onto the FPGA VI block diagram. If you click a target-scoped FIFO and drag it onto the block diagram, LabVIEW places a FIFO Write function, configured for the target-scoped FIFO, onto the block diagram. If you click a DMA FIFO and drag it onto the block diagram, LabVIEW places a FIFO Write function, configured for the DMA FIFO, on the block diagram.
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Note If you use the FIFO Read and FIFO Write functions in a single-cycle Timed Loop, you must wire a constant of zero to the Timeout parameter. |
Refer to Reading DMA FIFOs from Host VIs and Writing to DMA FIFOs from Host VIs for more information about using DMA FIFOs in host VIs.