Controlling the FPGA VI Execution Rate (FPGA Module)
The top-level clock on an FPGA target determines the execution time of the individual functions and VIs on the FPGA VI block diagram. If you change the execution speed on the top-level clock, you also change the operation speed of functions on the block diagram. When you change the operation speed on the block diagram, you also change the execution rate of the FPGA VI. If the FPGA target allows, you can configure the FPGA base clock and set it as the top-level clock in the project to control execution rates. If the FPGA target does not allow you to configure the FPGA base clock the way you want, you can use a derived clock. Support of FPGA derived clocks varies by FPGA target. Refer to the specific FPGA target hardware documentation for more information.
Complete the following steps to create an FPGA derived clock to control the execution rate of items on the block diagram.
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Note If you use a base clock or derived clock for the single-cycle Timed Loop, the code inside the single-cycle Timed Loop executes at the base clock or derived clock rate. If you configure an FPGA base clock or create a derived clock and set it as the top-level clock, you control the execution rate of the code outside of the single-cycle Timed Loop. |
- Create a new project or open an existing project.
- Add an FPGA target to the project.
- Create an FPGA derived clock.
- Configure the FPGA derived clock to run at the execution rate you want.
- Set the FPGA derived clock as the top level clock.
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Note Some FPGA VIs cannot be compiled with faster clock rates. The complexity of the FPGA VI can affect the execution rate on the FPGA target. If you select a clock rate that is too fast for the FPGA VI, the Compilation Failure dialog box returns a report that the compile failed. You can use a lower clock rate or rewrite the FPGA VI and try the compile again. |