Creating FPGA FIFOs (FPGA Module)
The FPGA Module includes the following types of FIFOs:
- Target–scoped FIFOs—Use to transfer data to and from loops. Use target–scoped FIFOs if you want to create a single FIFO that you can use in multiple VIs. You also can use target–scoped FIFOs to transfer data from one subVI to another in an FPGA VI. If you send an FPGA VI with a target-scoped FIFO to another user, you must also send the project. Otherwise, the FPGA VI is broken.
- VI–scoped FIFOs—Use to transfer data to and from loops. Use VI-scoped FIFOs if you want to create a FIFO that you can use only within a single VI. If you send an FPGA VI with a VI-scoped FIFO to another user, you do not need to send the LabVIEW project because the FIFO does not include a corresponding item in the Project Explorer window. If you use a VI-scoped FIFO in a reentrant FPGA VI, LabVIEW creates a separate copy of the FIFO for each instance of the VI, which allows you to create reusable subVIs while avoiding resource conflicts.
- Direct Memory Access (DMA) FIFOs—Use to transfer data to and from host VIs.
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Note Some FPGA targets do not support DMA FIFOs. Refer to the specific FPGA target hardware documentation for more information. |
Complete the following steps to create a FIFO.
- Create a new project or open an existing project.
- Add an FPGA target to the project.
- Determine whether you want to create a target-scoped, VI-scoped, or DMA FIFO.
- To create a target-scoped or DMA FIFO, right-click the FPGA target in the Project Explorer window and select New»FIFO from the shortcut menu. The FPGA FIFO Properties dialog box appears.
- To create a VI-scoped FIFO, place a VI-Scoped FIFO Configuration node on the block diagram, right-click the node, and select Properties from the shortcut menu. The FPGA FIFO Properties dialog box appears.
- Configure the FIFO item in the FPGA FIFO Properties dialog box. Select Target-Scoped from the Type pull-down menu if you want to use a target-scoped FIFO. Select Host to Target—DMA or Target to Host—DMA from the Type pull-down menu if you want to use a DMA FIFO.
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Note If you use a FIFO Read or FIFO Write function configured with a FIFO in a single-cycle Timed Loop, make sure the corresponding arbitration option is Arbitrate if Multiple Requestors Only or Never Arbitrate. Also, do not use the FIFO Read or the FIFO Write function configured with the same FPGA FIFO you use in the single-cycle Timed Loop in other locations on the block diagram. |
Refer to Reading DMA FIFOs from Host VIs and Writing to DMA FIFOs from Host VIs for more information about using DMA FIFOs in host VIs.