Debugging FPGA VIs (FPGA Module)
If an FPGA VI is not broken, but you get unexpected data, you can use the following techniques to identify and correct problems with the FPGA VI or the block diagram data flow:
- Add indicators to the FPGA VI block diagram to monitor the internal state of the FPGA VI. Use indicators instead of probes. Place indicators anywhere on the block diagram where you need to see data to verify the functionality of the VI.
- Add I/O to the FPGA VI block diagram. If you have unused I/O resources on the FPGA target, you can use the unused resources to monitor the internal state of Boolean logic, triggers, and so on.
- Run the FPGA VI on the development computer. You can use all traditional LabVIEW debugging techniques, such as probes, execution highlighting, breakpoints, and single-stepping. You cannot test certain behavior, such as timing and determinism.