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Compiling an FPGA VI can take minutes to hours. You can test the logic of an FPGA VI before compiling it by running the FPGA VI on a development computer with simulated I/O. When you run an FPGA VI on a development computer with simulated I/O, LabVIEW generates random data for the inputs or uses a custom VI that you create to provide I/O. On some FPGA targets, you also can run the FPGA VI on a development computer with real I/O.

Complete the following steps to test an FPGA VI on a development computer.

1. Create a new project or open an existing project.
2. Add an FPGA target to the project.
3. Create a new VI or open an existing VI under the FPGA target.
4. Right-click the FPGA target in the Project Explorer window and select Properties from the shortcut menu. The FPGA Target Properties dialog box appears.
5. Select Debugging from the Category list to display the Debugging Properties page.
6. Select one of the following options:
   • Execute VI on Development Computer with Simulated I/O—If you select this option, select Use Random Data for I/O Read or Use Custom VI for FPGA I/O from the pull-down menu.
   • Execute VI on Development Computer with Real I/O—Some FPGA targets do not support this option.
7. If you select Use Custom VI for FPGA I/O in the previous step, specify the path to the custom VI using the VI Path control. LabVIEW calls the VI you specify whenever FPGA I/O Nodes, FPGA I/O Property Nodes, or FPGA I/O Method Nodes execute on the block diagram on the FPGA VI.
8. Click the OK button.
9. Click the Run button on the FPGA VI.
10. (Optional) Right-click the FPGA VI in the Project Explorer window and select Compile from the shortcut menu. You should compile the FPGA VI periodically to verify that the FPGA VI meets requirements.

You also can change where the FPGA VI executes by right-clicking the FPGA target in the Project Explorer window and selecting an option from the Execute VI on shortcut menu.

You can use all traditional LabVIEW debugging techniques, such as probes, execution highlighting, breakpoints, and single-stepping. You cannot test certain behavior, such as timing and determinism.

Note  You can use a host VI to communicate with an FPGA VI running on a development computer with simulated I/O. However, you must be aware of special considerations when using the host VI.

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