Version 8.6 Features (FPGA Module)
Refer to the LabVIEW 8.6 Features and Changes topic for information about new features in LabVIEW 8.6.
Refer to the LabVIEW FPGA Release and Upgrade Notes for a complete list of new features and changes, as well as information about upgrade and compatibility issues specific to different versions of the FPGA Module. Refer to the readme_fpga.html file in the LabVIEW 8.6\readme directory for information about known issues with the FPGA Module 8.6.
The FPGA Module 8.6 includes the following new features to help you better manage and implement the components of an FPGA application.
Improved Debugging and Test Bench Capabilities
- Simulating I/O—In the FPGA Module 8.6, you can test the logic of an FPGA VI by executing the FPGA VI on the development computer using simulated I/O. In addition to using random data for inputs, you can create a custom VI for read and write operations of FPGA I/O Nodes, FPGA I/O Method Nodes, and FPGA I/O Property Nodes. With the custom VI, you can control values that the FPGA VI reads and monitor values that the FPGA VI writes.
- Using Host VIs to Test FPGA VIs—In the FPGA Module 8.5.x and earlier, the host VI controls only the FPGA VI on the FPGA target. In the FPGA Module 8.6, you can use the host VI to control the FPGA VI running on the development computer. Therefore, you can test more of the functionality of the FPGA VI than was possible in previous versions of the FPGA Module. In particular, you can test interactions of the FPGA VI with the host VI by reading and writing controls, handling interrupts, and using DMA FIFOs. You now can repeat tests of FPGA VI and host VI interactions. Refer to the Communicating with an FPGA VI Running on a Development Computer topic for special considerations.
FIFO and Memory Improvements
- Fixed-Point Support for FIFO and Memory Items—In the FPGA Module 8.6, FIFO and memory items support the fixed-point data type. Use the FPGA FIFO Properties dialog box to configure a FIFO item to use the fixed-point data type. Use the Memory Properties dialog box to configure a memory item to use the fixed-point data type.
- Additional Data Type Support for DMA FIFOs—In the FPGA Module 8.5.x and earlier, Direct Memory Access (DMA) FIFOs support only the U32 data type. In the FPGA Module 8.6, DMA FIFOs also support Boolean, fixed-point, and all integer data types. Use the FPGA FIFO Properties dialog box to configure the data type for the DMA FIFO.
- Automatic DMA Channel Allocation—In the FPGA Module 8.5.x and earlier, you must specify the DMA channel to use on the FPGA target. In the FPGA Module 8.6, the FPGA target selects the DMA channel automatically.
Math and Analysis VIs
- New VIs—The FPGA Module 8.6 includes the Rational Resampler, Scaled Window, and FFT VIs.
- Fixed-Point Support—The FPGA Module 8.6 includes support for the fixed-point data type in the following VIs: Backlash, Dead Zone, Discrete Control Filter, Discrete Normalized Integration, Friction, Initial Condition, Linear Interpolation, Memory Element, Rate Limiter, Relay, Switch, Trigger, Unit Delay, Zero Crossing, and Zero-Order Hold.
Additional Functions on the FPGA Numeric Functions Palette
The FPGA Numeric palette now includes the Divide, Reciprocal, and Square Root functions, which support the fixed-point data type.
Running HDL Code on FPGAs alongside FPGA VIs
In the FPGA Module 8.6, some FPGA targets support using component-level IP (CLIP) to instantiate HDL code with a defined interface that occupies a portion of an FPGA.
Improved Performance Using External Clocks
Some FPGA targets support using a digital I/O resource as an external clock. External clocks enable tighter synchronization with external hardware and, in some cases, better performance than onboard clocks, which require additional overhead for synchronization. You can use an external clock as the clock for a single-cycle Timed Loop.