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Owning Palette: FPGA Math & Analysis VIs and Functions

Requires: FPGA Module

Filters one or more input signals using a lowpass or highpass IIR Butterworth filter.

The filter can be of order 1, 2, or 4.

You can use the Butterworth Coefficients Express VI to generate the set of filter coefficients during run time.

Details  

Dialog Box Options

Block Diagram Inputs

Block Diagram Outputs

Dialog Box Options

Parameter	Description
Filter Specifications	Contains the following options: Type—Specifies whether the filter type is Lowpass or Highpass. Cutoff frequency (Hz)—Specifies the cutoff frequency of the filter. The allowable frequency range depends on the Expected sample rate you specify. The normalized cutoff frequency (Cutoff frequency/Expected sample rate) must be less than 0.5, which corresponds to the Nyquist frequency. Expected sample rate (S/s)—Specifies the sample rate, in samples per second, of the input signal. This Express VI uses the rate you specify to calculate the normalized cutoff frequency, which is Cutoff frequency/Expected sample rate. Caution  The actual sample rate is specified elsewhere in the FPGA application. If the sample rate changes, you must change the Expected sample rate in this VI. Otherwise, this VI might not behave as expected. Order—Specifies the filter order. You can select 1 (first-order), 2 (second-order), or 4 (fourth-order).
Output Data Type	Contains the following options: Avoid overflow—Specifies that the word length and integer word length of the output data type are large enough to ensure that the filter output does not overflow. Same as input—Specifies that the output data type is the same as the input data type. The output will saturate if the output range is exceeded during signal transients. Overflow will not occur with a steady-state sinusoidal input.
Implementation	Contains the following options: Number of channels—Specifies the number of channels of input data to process. The calling VI must supply a sequential channel scan to input data on successive calls to this Express VI. The channel order must be fixed. FPGA clock rate (MHz)—Specifies the design clock rate at which the LabVIEW FPGA Compile Server compiles the FPGA VI. If the FPGA clock rate parameter does not match the top-level clock rate, the Code Generation Errors window returns an error when you compile the FPGA VI. Use the Top-Level Clock FPGA Target Properties page to change the top-level clock rate.
Filter Response	Displays the actual magnitude response of the filter.

Block Diagram Inputs

Parameter	Description
reset	Resets the filter states of the input data channel to zero if TRUE. Resetting the filter states does not reset the filter coefficients. This input is available only when you place a checkmark in the Show reset terminal checkbox on the configuration dialog box.
input data	Specifies the input signal to filter. input data is a fixed-point number or integer with a maximum word length of 32 bits.
scaled coefficients	Specifies single-channel filter coefficients to load at run time. Scaled coefficients is a fixed-size array of 32-bit signed integers. The size of the array depends on the order you specify. If the filter order is one, the array contains two elements. If the filter order is two, the array contains three elements. If the filter order is four, the array contains six elements.The filter coefficients must correspond to the filter type and order you specify using the Type and Order options. You cannot alter the order or type of the filter at run time.This parameter is available only when you configure the VI for single-channel input and place a checkmark in the Show configuration terminal checkbox on the configuration dialog box.
configuration	Specifies the scaled coefficients to load at run time for the channel index you specify using the channel index element of this cluster. This Express VI continues to use either the default coefficients or the last coefficients you specified for the channel until you specify new coefficients. This parameter is available only when you configure the VI for multi-channel input and place a checkmark in the Show configuration terminal checkbox on the configuration dialog box.

Block Diagram Outputs

Parameter	Description
output data	Returns the filtered signal corresponding to the input data channel.

Butterworth Filter Details

Refer to the Developer Zone for more information about the accuracy of the FPGA Math and Analysis VIs.