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Owning Palette: FPGA Math & Analysis VIs and Functions

Requires: FPGA Module

Computes the Fast Fourier Transform (FFT) point by point. Use this Express VI after you use the Scaled Window Express VI to minimize spectral leakage associated with truncated waveforms. Use the FFT to Spectrum VI to convert the output of the FFT Express VI to an amplitude or power spectrum.

Details  

Dialog Box Options

Block Diagram Inputs

Block Diagram Outputs

Dialog Box Options

Parameter	Description
Transform Parameters	Contains the following options: Length—Specifies the length, also known as the frame size, of the transform the Express VI calculates. Valid options are powers of two between 8 and 8192. Direction—Specifies whether to calculate a forward or inverse (IFFT) transform.
Output Data Type	Contains the following options: Adapt to source—Specifies whether the Express VI decides the output data type. Do not place a checkmark in this checkbox if you want to use the Word length control to determine the output data type. Word length—Specifies any output word length in the range of [8, 32]. This control is available only if you did not place a checkmark in the Adapt to source checkbox. Output Word length must be between input Word length and 32 if the input is signed. Output Word length must be between input Word length + 1 and 32 if the input is unsigned. Tip  Decreasing the output Word length saves resources but also reduces precision. National Instruments recommends that you simulate the configuration you are considering to ensure that the precision you achieve meets your needs. Integer word length—Indicates the output integer word length that the Express VI calculates.
Execution Mode	Contains the following options: Outside single-cycle Timed Loop—Select this option when you want to use this Express VI outside of a single-cycle Timed Loop. Using this Express VI outside the single-cycle Timed Loop produces a latency of 2 x Length, which means that it takes two times Length calls to the Express VI before a valid output bin is returned. After the initial latency, the Express VI returns a valid output bin every time it is called. Inside single-cycle Timed Loop—Select this option when you want to use this Express VI inside a single-cycle Timed Loop. Selecting Inside single-cycle Timed Loop enables the Throughput option. When you execute this Express VI inside the single-cycle Timed Loop, you can use the handshaking signals to schedule the timing of data. Clock rate—Specifies the maximum clock rate at which this function can compile. A faster clock rate requires more internal pipelining stages, which increases the FPGA resource usage and the Latency of this function. An increased Latency means this function takes longer to return a valid result. Throughput—Specifies the minimum number of cycles between two successive frames of valid input data. This option is available only if you select Inside single-cycle Timed Loop. If you select Outside single-cycle Timed Loop, LabVIEW sets the throughput to 1 call / sample, which means this Express VI can accept data every time it is called. Tip  Entering a low value in this control results in a high throughput rate. However, setting Throughput to 1 consumes several times more resources. , so you should only select 1 if you need higher throughput. Latency—Indicates the latency associated with the configuration you select.

Block Diagram Inputs

Parameter	Description
reset	Clears all internal states on the cycle or call for which this signal is TRUE. Outside the single-cycle Timed Loop, the Express VI restarts on the same call that reset is TRUE. Inside the single-cycle Timed Loop, the Express VI restarts on the first call that reset is deasserted after reset is TRUE. Additionally, the handshaking signals behave as follows during the cycles where reset is asserted: input valid is ignored. ready for output is ignored. output valid is FALSE. ready for input is FALSE, which handles cases where reset is held TRUE for a long time. The Express VI is not ready for inputs when reset is asserted.
real data in	Specifies the real part of the input signal.
imaginary data in	Specifies the imaginary part of the input signal. Leave this terminal unwired to read only real data.
input valid	Specifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.To display this handshaking terminal, select the Inside single-cycle Timed Loop option in the configuration dialog box.
ready for output	Specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node. Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle. To display this terminal, select the Inside single-cycle Timed Loop option in the configuration dialog box.

Block Diagram Outputs

Parameter	Description
data index	Indicates which FFT bin the VI is outputting.
real data out	Returns the real part of the FFT result.
imaginary data out	Returns the imaginary part of the FFT result.
output valid	Returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.
ready for input	Returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node. Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the input valid terminal is TRUE during the following cycle. To display this terminal, select the Inside single-cycle Timed Loop option in the configuration dialog box.

FFT Details

Timing Diagram Outside the Single-Cycle Timed Loop

The following diagram demonstrates timing when you use this Express VI outside of a single-cycle Timed Loop.

Timing Diagram Inside the Single-Cycle Timed Loop when Throughput is Equal to 1

The following diagram demonstrates timing when you use this Express VI inside a single-cycle Timed Loop with Throughput equal to 1.

Timing Diagram Inside the Single-Cycle Timed Loop when Throughput is Not Equal to 1

The following diagram demonstrates timing when you use this Express VI inside a single-cycle Timed Loop with Throughput not equal to 1.

Avoiding Data Loss During FFT Calculation

In a single-cycle Timed Loop, the FFT Express VI does not accept or return values while computing the FFT. During this time, if the system or another node sends data to this Express VI, LabVIEW discards the data. This might happen if the FFT Express VI receives data as part of a complicated, or non-uniform, pattern.

To ensure no data is lost, create a FIFO to hold data until this Express VI accepts values again. Ensure that the FIFO you create is large enough to hold all data points that collect during the FFT calculation time. To roughly estimate the size of the FIFO you need to create, divide the latency of the FFT Express VI by the average system throughput.