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Owning Palette: High Throughput Math Functions

Requires: FPGA Module

Computes the quotient of x and y. This function rounds the result by truncating the value of the x/y output terminal towards 0. This rounding mode uses fewer FPGA resources than other rounding modes do.

This function supports only the fixed-point data type.

Details  

Dialog Box Options

Block Diagram Inputs

Block Diagram Outputs

Dialog Box Options

Parameter	Description
Fixed-Point Configuration	Specifies the encodings, word lengths, and integer word lengths of the input and output terminals of this function. The configurations you specify determine the value range of the terminals. x Type—Specifies the fixed-point configuration of the x input terminal. If you wire a fixed-point data type to this terminal, LabVIEW dims this section and uses information from the wire. Signed—Specifies that this terminal is signed. Unsigned—Specifies that this terminal is unsigned. Word length—Specifies the word length of this terminal. Integer word length—Specifies the integer word length of this terminal. y Type—Specifies the fixed-point configuration of the y input terminal. If you wire a fixed-point data type to this terminal, LabVIEW dims this section and uses information from the wire. Signed—Specifies that this terminal is signed. Unsigned—Specifies that this terminal is unsigned. Word length—Specifies the word length of this terminal. Integer word length—Specifies the integer word length of this terminal. x/y Type—Specifies the fixed-point configuration of the x/y output terminal. Adapt to source—Specifies whether LabVIEW automatically adjusts the fixed-point configuration of the output data type to avoid overflow for nonzero values of y. By default, this checkbox contains a checkmark and LabVIEW dims the following options. Note  Because the precision of the quotient might be infinite, rounding errors always occur. Signed—Specifies that this terminal is signed. LabVIEW sets the encoding of this terminal based on the encoding of the input terminals and dims this option. Unsigned—Specifies that this terminal is unsigned. LabVIEW sets the encoding of this terminal based on the encoding of the input terminals and dims this option. Word length—Specifies the word length of this terminal. Integer word length—Specifies the integer word length of this terminal. Include overflow status—Specifies whether the output terminal includes the overflow status. You can propagate this status to downstream nodes. Including this status requires additional FPGA resources. By default, this checkbox does not contain a checkmark. If you place a checkmark in this checkbox, the overflow status becomes TRUE in either of the following situations: The overflow status of an input terminal is TRUE. Overflow occurs during the operation of this function. If you place a checkmark in the Adapt to source checkbox, LabVIEW sets Include overflow status depending on whether an input terminal includes this status. Overflow mode—Specifies how this function handles overflow. You can choose from the following options: Saturate (default)—Specifies that if overflow occurs, this function saturates the x/y output terminal. Note  If you select Saturate and the value of y is 0, this function uses the following equations to determine the value of the x/y output terminal. x/y = max(x/y), if x ≥ 0 x/y = min(x/y), if x < 0 Undefined result—Specifies that if overflow occurs, the value of the x/y output terminal is undefined. Note  The Undefined result option does not require any additional FPGA resources. Conversely, the Saturate option requires additional FPGA resources and a longer combinatorial path, which might decrease the maximum clock rate this function can achieve.
Execution Mode	Specifies how this function executes. Outside single-cycle Timed Loop—Configures this function to execute outside a single-cycle Timed Loop. If you select this option and place this function inside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI. Inside single-cycle Timed Loop—Configures this function to execute inside a single-cycle Timed Loop. If you select this option and place this function outside a single-cycle Timed Loop, the Code Generation Errors window reports an error when you compile the FPGA VI. Throughput—Specifies the minimum number of cycles between two successive values of valid input data. Entering a low value in this control results in a high throughput rate. The maximum value of Throughput depends on the Word length of the output terminal. This option is available only if you select Inside single-cycle Timed Loop. If you select Outside single-cycle Timed Loop, this function returns a valid result on every call to the function. Therefore, the Throughput control displays 1 call / sample. The Configuration Feedback indicator displays the number of clock cycles this function takes to return a valid result.
Registers	Specifies whether to add internal registers for function inputs and/or outputs. This section is available only if you select Inside single-cycle Timed Loop. Note  Adding registers can reduce the length of the combinatorial path, which can prevent compilation errors that result from a long combinatorial path. However, adding registers also increases the latency of this function, which means this function takes additional clock cycles to return a valid result. Register inputs—Adds internal registers after the inputs to this function. Selecting this option increases the latency of the function by one cycle. Register outputs—Adds internal registers before the outputs of this function. Selecting this option increases the latency of the function by one cycle.
Optional Terminal	Specifies a setting for displaying an optional block diagram terminal. Operation overflow—Specifies that this function displays the operation overflow output terminal on the block diagram. This terminal indicates whether overflow occurred during the operation of this function.
Configuration Feedback	Displays information about how this function executes. This information is based on the configuration options you specify.

Block Diagram Inputs

Parameter	Description
x	Specifies the dividend.
y	Specifies the divisor. If the value of y is 0, overflow occurs in the x/y output terminal.
input valid	Specifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node. To display this handshaking terminal, select the Inside single-cycle Timed Loop option in the configuration dialog box.
ready for output	Specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node. Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle. To display this terminal, select the Inside single-cycle Timed Loop option in the configuration dialog box.

Block Diagram Outputs

Parameter	Description
x/y	Returns x divided by y.
operation overflow	Returns TRUE if the theoretical computed value exceeds the valid range of the output data type. If operation overflow returns TRUE, the Overflow mode option determines the value this function returns. LabVIEW displays the operation overflow terminal only if you place a checkmark in the Operation overflow checkbox. This checkbox is located in the Optional Terminal section of the configuration dialog box.
output valid	Returns TRUE if this node has computed a result that downstream nodes can use. Use this terminal for handshaking with other FPGA VIs and functions. To display this terminal, select the Inside single-cycle Timed Loop option in the configuration dialog box.
ready for input	Returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node. Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the input valid terminal is TRUE during the following cycle. To display this terminal, select the Inside single-cycle Timed Loop option in the configuration dialog box.

High Throughput Divide Details

If you place a checkmark in the Adapt to source checkbox, overflow still can occur in the x/y output terminal for non-zero values of y if both of the following conditions are true:

• x = –2^{iwl_x – 1}
• y = –2^{iwl_y – wl_y}

where wl refers to the word length of a terminal and iwl refers to the integer word length of a terminal.

Complete the following steps to avoid overflow in this situation and for any non-zero value of y.

1. Remove the checkmark from the Adapt to source checkbox.
2. Increase both the Word length and Integer word length of the x/y terminal by at least 1 bit.

After you complete these steps, LabVIEW does not adjust the fixed-point configuration of the x/y terminal automatically. If you change the fixed-point configuration of the x or y terminal and still want to avoid overflow for any non-zero value of y, place a checkmark in the Adapt to source checkbox again. LabVIEW adjusts the fixed-point configuration of the x/y terminal automatically. Then, complete steps 1–2 above to ensure that no overflow occurs with the updated fixed-point configurations.