Using the LabVIEW FPGA Compile Server (FPGA Module)

You use the LabVIEW FPGA Compile Server to compile FPGA VIs. LabVIEW and the LabVIEW FPGA Compile Server have a client-server architecture, where LabVIEW is a client to the LabVIEW FPGA Compile Server. The client-server architecture allows you to disconnect LabVIEW from the LabVIEW FPGA Compile Server so that you can queue up multiple VIs to compile. You can continue to use LabVIEW while the FPGA VI compiles, but you must not modify the FPGA VI being compiled.

LabVIEW displays compilation reports in the Compilation Status window during compilation. You can view the reports if you are connected to the LabVIEW FPGA Compile Server. If the FPGA target you use supports Interactive Front Panel Communication, LabVIEW downloads the bitstream to the FPGA when the compilation server is done compiling and the compilation is successful. The FPGA VI then runs on the FPGA target, and you can interact with the VI through the front panel window on the host computer.

The LabVIEW FPGA Compile Server does not close automatically. Close it by clicking the Stop Server button.

How the Compilation Process Works

LabVIEW converts the VI into intermediate files to send to the LabVIEW FPGA Compile Server. The compilation server uses Xilinx to convert the intermediate files into a bitstream. The process of converting the intermediate files goes through the following steps.

1. HDL compilation, analysis, and synthesis—Transforms intermediate files (HDL code) into digital logic elements.
2. Mapping—Divides the application logic between the physical building block on the FPGA.
3. Placing and Routing—Assigns the logic to physical building blocks on the FPGA and routes the connections between the logic blocks to meet the space or timing constraints of the compilation.
4. Generating bitstream—Creates binary data that LabVIEW saves inside a bitfile.

LabVIEW saves the bitfile in a subdirectory of the project directory. When you run an FPGA VI using Interactive Front Panel Communication, LabVIEW automatically downloads the bitfile corresponding to the VI to the FPGA target. You also can use the bitfile to distribute an FPGA VI to a LabVIEW user without the FPGA Module.

Note   The availability of Interactive Front Panel Communication varies by FPGA target. Refer to the specific hardware documentation for information about using Interactive Front Panel Communication.

The compilation time depends on the size of the VI, the processor speed, and amount of memory in the computer on which you are compiling. If the computer does not have sufficient memory, smaller block diagrams might compile quickly, but larger block diagrams might use large amounts of virtual memory, which can cause compilations to fail or take over 10 times longer to complete.

Compiling on a Remote Computer

You can install the LabVIEW FPGA Compile Server on a remote computer. You might want to do this if the development computer is slow and does not have enough memory to compile for the FPGA target. However, by default, LabVIEW assumes the LabVIEW FPGA Compile Server is installed on the development computer. To select a remote LabVIEW FPGA Compile Server, select Tools»FPGA Module Options to display the FPGA Module Options dialog box. Enter the name or IP address of the remote computer running the LabVIEW FPGA Compile Server. Depending on the network, you also might need to increase the network timeout.

Note  Prior to compiling on a remote computer, you must manually launch the LabVIEW FPGA Compile Server on the remote computer by selecting Start»All Programs»National Instruments»LabVIEW»LabVIEW FPGA Utilities»Compile Server.

Managing Compilation Files

The LabVIEW FPGA Compile Server stores all files it uses to compile a VI in one directory. Configure the directory by clicking the Configure button in the LabVIEW FPGA Compile Server window. Click the Compile List button to view the compilation history and delete compiled files you no longer need. Typically, you do not need compiled files after the bitfile is created. To save space on the hard drive, you can periodically delete the contents of Z :\NIFPGA x \clntTmp and Z :\NIFPGA x \srvrTmp, where Z is the drive on which you installed LabVIEW and the FPGA Module and x is the version of the FPGA Module you are using.