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Using External Clocks for Synchronous Design (FPGA Module)

LabVIEW 2009 FPGA Module Help

Edition Date: June 2009

Part Number: 371599E-01

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Some FPGA targets support using a digital I/O resource as an external clock. External clocks are useful for synchronous design because they enable tighter synchronization and better performance for some digital protocols. The following illustration shows a synchronous system that passes data between an FPGA target and external device.

A synchronous system can include several delays, including the following:

  • Clock skew—Delays from the clock source to the flip-flops, which are circuits capable of two stable states. For example, the amount of time for the clock in the illustration above to reach each flip-flop might vary.
  • Data path delay—Delays along the data path. For example, the data path can include the time it takes the data signal to go between the FPGA target and external device in the illustration above.

You must balance these delays against the setup and hold requirements of the destination flip-flop.

Meeting Setup and Hold Requirements to Ensure Valid Data

The synchronous inputs to a flip-flop must be stable during the setup time and hold time to guarantee data integrity. The setup time specifies how long the data needs to be stable before the clock edge. The hold time specifies how long the data needs to be stable after the clock edge. The clock edge is the period when a flip-flop stores data. The FPGA target defines the setup and hold requirements.

CautionIf you miss setup and hold requirements on flip-flops in the external clock domain, metastable data might be available on the block diagram. If data is metastable, the FPGA Module cannot guarantee synchronous circuit behavior and unpredictable execution might result. If you notice incorrect execution, redownload the FPGA VI.

The following illustration shows an example of the setup and hold requirements for a flip-flop. In this illustration, the hold time occurs after the rising clock edge. However, with some FPGA targets, the hold time occurs before the rising clock edge, so the hold time is negative.

Use the clock-to-out time to check for hold and setup violations. The clock-to-out time specifies how long it takes from a clock edge for an output to change on an output pin. When checking for hold violations, consider factors that get data to the destination flip-flop as soon as possible. Use the minimum clock-to-out time to verify that you did not miss the hold requirement for the destination. When checking for setup violations, consider factors that get data to the destination flip-flop as late as possible. Use the maximum clock-to-out time to verify that you did not miss the setup requirement for the destination.

Configuring FPGA I/O for External Clocks

In some cases, delays in the data path can cause a hold violation because the destination flip-flop does not receive the data at the expected clock edge. In such cases, you can select a different clock edge to avoid a hold violation. Use the Advanced Code Generation FPGA I/O Properties page to specify if the synchronizing register(s) should use a rising or falling clock edge for output data, output enable, and/or reading. In general, you should transmit on one clock edge and receive on the opposite clock edge.

Using an External Clock in a Single-Cycle Timed Loop

You can use an external clock only in a single-cycle Timed Loop. You cannot use an external clock as a top-level clock.

To avoid transferring invalid data, do not wire a stop condition to the stop terminal of the single-cycle Timed Loop. If you do wire a stop condition, the FPGA Module returns a code generation error.

Enabling and Disabling External Clocks

A clock with glitches can cause incorrect execution. A clock with glitches has at least one period less than the configured period checked by static timing analysis. Therefore, the clock does not allocate enough time for the logic between two flip-flops to execute. If you know a clock contains glitches during a specific period, you must disable the clock during that period to avoid incorrect execution.

Circuitry controlled by an FPGA VI is dependent on a periodic clock. Use the Start Enabling FPGA Clock and Start Disabling FPGA Clock VIs to protect circuitry when the periodic clock might not be available. You can include the VIs in a Case structure, as shown in the following block diagram, to ensure the VIs do not execute simultaneously. If the VIs execute simultaneously, the clock is enabled. The Case structure includes a separate case for the Start Disabling FPGA Clock VI and Start Enabling FPGA Clock VI. You must include the VIs in a clock domain other than the clock domain you want to disable.

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